| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_lspcon.c | 334 ret = drm_dp_dpcd_write(aux, reg, data, 8); in _lspcon_parade_write_infoframe_blocks()
349 ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1); in _lspcon_parade_write_infoframe_blocks()
408 ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1); in _lspcon_write_avi_infoframe_mca()
434 ret = drm_dp_dpcd_write(aux, reg, &val, 1); in _lspcon_write_avi_infoframe_mca()
|
| A D | intel_dp_link_training.c | 122 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; in intel_dp_set_lttpr_transparent_mode()
462 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; in intel_dp_set_link_train()
579 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, in intel_dp_update_link_train()
671 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); in intel_dp_prepare_link_train()
675 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, in intel_dp_prepare_link_train()
681 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); in intel_dp_prepare_link_train()
1005 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; in intel_dp_disable_dpcd_training_pattern()
|
| A D | intel_dp_hdcp.c | 66 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, in intel_dp_hdcp_write_an_aksv()
82 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, in intel_dp_hdcp_write_an_aksv()
468 ret = drm_dp_dpcd_write(&dig_port->dp.aux, in intel_dp_hdcp2_write_msg()
|
| A D | intel_dp_aux_backlight.c | 179 if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, in intel_dp_aux_hdr_set_aux_backlight()
|
| A D | intel_dp.c | 1957 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) in intel_edp_init_source_oui()
3458 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, in intel_dp_process_phy_request()
3602 wret = drm_dp_dpcd_write(&intel_dp->aux, in intel_dp_check_mst_status()
|
| /linux/drivers/gpu/drm/ |
| A D | drm_dp_helper.c | 403 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, in drm_dp_dpcd_write() function
417 EXPORT_SYMBOL(drm_dp_dpcd_write);
586 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, in drm_dp_send_real_edid_checksum()
594 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, in drm_dp_send_real_edid_checksum()
602 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { in drm_dp_send_real_edid_checksum()
2418 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2); in drm_dp_set_phy_test_pattern()
3087 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); in drm_dp_pcon_pps_override_buf()
3112 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); in drm_dp_pcon_pps_override_param()
3115 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); in drm_dp_pcon_pps_override_param()
3118 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); in drm_dp_pcon_pps_override_param()
[all …]
|
| A D | drm_dp_cec.c | 114 err = drm_dp_dpcd_write(aux, DP_CEC_LOGICAL_ADDRESS_MASK, mask, 2); in drm_dp_cec_adap_log_addr()
125 err = drm_dp_dpcd_write(aux, DP_CEC_TX_MESSAGE_BUFFER, in drm_dp_cec_adap_transmit()
|
| A D | drm_dp_aux_dev.c | 214 res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo); in auxdev_write_iter()
|
| A D | drm_dp_mst_topology.c | 2223 ret = drm_dp_dpcd_write(mstb->mgr->aux, in drm_dp_check_mstb_guid()
2782 ret = drm_dp_dpcd_write(mgr->aux, regbase + offset, in drm_dp_send_sideband_msg()
4655 ret = drm_dp_dpcd_write(mgr->aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3); in drm_dp_dpcd_write_payload()
|
| /linux/drivers/gpu/drm/tegra/ |
| A D | dp.c | 351 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); in drm_dp_link_configure()
489 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, lanes); in drm_dp_link_apply_training()
502 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_1_SET2, values, in drm_dp_link_apply_training()
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_helpers.c | 528 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, in dm_helpers_dp_write_dpcd()
584 ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); in dm_helpers_dp_write_dsc_enable()
|
| A D | amdgpu_dm.c | 3123 wret = drm_dp_dpcd_write( in dm_handle_mst_sideband_msg()
|
| /linux/drivers/gpu/drm/bridge/analogix/ |
| A D | analogix_dp_core.c | 278 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); in analogix_dp_link_start()
319 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, in analogix_dp_link_start()
530 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, in analogix_dp_process_clock_recovery()
604 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, in analogix_dp_process_equalizer_training()
|
| A D | analogix-anx6345.c | 229 err = drm_dp_dpcd_write(&anx6345->aux, DP_LINK_BW_SET, dpcd, in anx6345_dp_link_training()
|
| A D | analogix-anx78xx.c | 736 err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd, in anx78xx_dp_link_training()
|
| /linux/drivers/gpu/drm/msm/edp/ |
| A D | edp_ctrl.c | 484 if (drm_dp_dpcd_write(ctrl->drm_aux, 0x103, buf, 4) < 4) { in edp_lane_set_write()
497 if (drm_dp_dpcd_write(ctrl->drm_aux, in edp_train_pattern_set_write()
767 if (drm_dp_dpcd_write(ctrl->drm_aux, DP_LINK_BW_SET, values, in edp_do_link_train()
|
| /linux/drivers/gpu/drm/bridge/ |
| A D | tc358767.c | 997 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2); in tc_main_link_enable()
1005 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); in tc_main_link_enable()
1012 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); in tc_main_link_enable()
|
| /linux/include/drm/ |
| A D | drm_dp_helper.h | 2026 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
2056 return drm_dp_dpcd_write(aux, offset, &value, 1); in drm_dp_dpcd_writeb()
|
| /linux/drivers/gpu/drm/msm/dp/ |
| A D | dp_ctrl.c | 96 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); in dp_aux_link_configure()
1036 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, in dp_ctrl_update_vx_px()
1241 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, in dp_ctrl_link_train()
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | atombios_dp.c | 510 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, in amdgpu_atombios_dp_update_vs_emph()
|
| /linux/drivers/gpu/drm/radeon/ |
| A D | atombios_dp.c | 561 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, in radeon_dp_update_vs_emph()
|
| A D | radeon_dp_mst.c | 706 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, in radeon_dp_mst_check_status()
|
| /linux/drivers/gpu/drm/bridge/cadence/ |
| A D | cdns-mhdp8546-core.c | 618 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); in cdns_mhdp_link_configure()
1460 drm_dp_dpcd_write(&mhdp->aux, DP_DOWNSPREAD_CTRL, amp, 2); in cdns_mhdp_link_up()
|
| /linux/drivers/gpu/drm/xlnx/ |
| A D | zynqmp_dp.c | 654 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
|
| /linux/drivers/gpu/drm/nouveau/dispnv50/ |
| A D | disp.c | 1476 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], in nv50_mstm_service()
|