Searched refs:ecc_ctrl (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | umc_v6_7.c | 295 uint32_t ecc_ctrl_addr, ecc_ctrl; in umc_v6_7_query_ras_poison_mode_per_channel() local
299 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
302 return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_EccCtrl, UCFatalEn); in umc_v6_7_query_ras_poison_mode_per_channel()
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| /linux/drivers/edac/ |
| A D | amd64_edac.h | 339 u32 ecc_ctrl; /* DRAM ECC Control reg */ member
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| A D | pnd2_edac.c | 437 static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS]; variable
493 if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) || in dnv_get_registers()
1101 if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) { in check_unit()
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| A D | amd64_edac.c | 1138 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in __dump_misc_regs_df()
3038 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
3041 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
3079 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in __read_mc_regs_df()
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