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Searched refs:gfx (Results 1 – 25 of 117) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_gfx.c68 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
98 adev->gfx.me.queue_bitmap); in amdgpu_gfx_is_me_queue_enabled()
134 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
255 adev->gfx.num_gfx_rings = in amdgpu_gfx_graphics_queue_acquire()
369 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_mqd_sw_init()
456 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_mqd_sw_fini()
635 if (!adev->gfx.ras_if) { in amdgpu_gfx_ras_late_init()
637 if (!adev->gfx.ras_if) in amdgpu_gfx_ras_late_init()
666 kfree(adev->gfx.ras_if); in amdgpu_gfx_ras_late_init()
667 adev->gfx.ras_if = NULL; in amdgpu_gfx_ras_late_init()
[all …]
A Damdgpu_rlc.c39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
107 src_ptr = adev->gfx.rlc.reg_list; in amdgpu_gfx_rlc_init_sr()
108 dst_ptr = adev->gfx.rlc.sr_ptr; in amdgpu_gfx_rlc_init_sr()
131 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
201 (adev->gfx.ce_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
209 (adev->gfx.pfp_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
217 (adev->gfx.me_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
225 (adev->gfx.mec_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
[all …]
A Dgfx_v7_0.c983 adev->gfx.me_fw = NULL; in gfx_v7_0_init_microcode()
985 adev->gfx.ce_fw = NULL; in gfx_v7_0_init_microcode()
1001 adev->gfx.me_fw = NULL; in gfx_v7_0_free_microcode()
1003 adev->gfx.ce_fw = NULL; in gfx_v7_0_free_microcode()
2069 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v7_0_scratch_init()
2461 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2724 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2807 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
3523 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
4366 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
[all …]
A Dgfx_v6_0.c386 adev->gfx.pfp_fw = NULL; in gfx_v6_0_init_microcode()
388 adev->gfx.me_fw = NULL; in gfx_v6_0_init_microcode()
390 adev->gfx.ce_fw = NULL; in gfx_v6_0_init_microcode()
392 adev->gfx.rlc_fw = NULL; in gfx_v6_0_init_microcode()
402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()
1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
1786 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v6_0_scratch_init()
1975 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v6_0_cp_gfx_load_microcode()
2381 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2526 if (!adev->gfx.rlc_fw) in gfx_v6_0_rlc_resume()
[all …]
A Dgfx_v9_0.c1027 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
1163 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1509 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v9_0_init_rlc_microcode()
1611 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; in gfx_v9_0_init_cp_compute_microcode()
1612 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; in gfx_v9_0_init_cp_compute_microcode()
2431 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
2731 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v9_0_init_csb()
3132 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
3216 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
3416 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
[all …]
A Dgfx_v8_0.c842 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
942 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
944 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
946 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
948 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
950 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
1118 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1222 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1844 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
2067 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
[all …]
A Dgfx_v10_0.c3807 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
3949 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3951 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
4191 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v10_0_init_microcode()
4921 kiq = &adev->gfx.kiq; in gfx_v10_0_sw_init()
5304 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v10_0_init_csb()
5389 if (!adev->gfx.rlc_fw) in gfx_v10_0_rlc_load_microcode()
5620 adev->gfx.ce_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5630 adev->gfx.me_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
6183 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
[all …]
A Damdgpu_atomfirmware.c644 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
645 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
648 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
649 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
651 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
653 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
658 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size); in amdgpu_atomfirmware_get_gfx_info()
662 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
663 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
666 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
[all …]
A Damdgpu_kms.c305 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
309 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
313 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
317 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
334 fw_info->ver = adev->gfx.mec_fw_version; in amdgpu_firmware_info()
337 fw_info->ver = adev->gfx.mec2_fw_version; in amdgpu_firmware_info()
432 if (adev->gfx.gfx_ring[i].sched.ready) in amdgpu_hw_ip_info()
827 adev->gfx.config.max_shader_engines; in amdgpu_info_ioctl()
863 sizeof(adev->gfx.cu_info.bitmap)); in amdgpu_info_ioctl()
868 adev->gfx.config.double_offchip_lds_buf; in amdgpu_info_ioctl()
[all …]
A Damdgpu_amdkfd.c138 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
145 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
146 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
372 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
375 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
378 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
381 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
384 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
387 return adev->gfx.rlc_fw_version; in amdgpu_amdkfd_get_fw_version()
435 if (adev->gfx.funcs->get_gpu_clock_counter) in amdgpu_amdkfd_get_gpu_clock_counter()
[all …]
A Damdgpu_discovery.c549 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
552 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
555 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
560 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); in amdgpu_discovery_get_gfx_info()
563 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); in amdgpu_discovery_get_gfx_info()
569 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); in amdgpu_discovery_get_gfx_info()
570 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); in amdgpu_discovery_get_gfx_info()
571 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
574 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
579 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); in amdgpu_discovery_get_gfx_info()
[all …]
A Damdgpu_amdkfd_gfx_v9.c180 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
181 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
321 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
331 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
336 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
363 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
834 max_queue_cnt = adev->gfx.mec.num_pipe_per_mec * in kgd_gfx_v9_get_cu_occupancy()
835 adev->gfx.mec.num_queue_per_pipe; in kgd_gfx_v9_get_cu_occupancy()
836 sh_cnt = adev->gfx.config.max_sh_per_se; in kgd_gfx_v9_get_cu_occupancy()
837 se_cnt = adev->gfx.config.max_shader_engines; in kgd_gfx_v9_get_cu_occupancy()
[all …]
A Damdgpu_ucode.c519 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
520 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
521 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
522 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
526 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
527 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
611 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; in amdgpu_ucode_init_single_fw()
615 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; in amdgpu_ucode_init_single_fw()
619 ucode_addr = adev->gfx.rlc.save_restore_list_srm; in amdgpu_ucode_init_single_fw()
623 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; in amdgpu_ucode_init_single_fw()
[all …]
A Damdgpu_debugfs.c733 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
734 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
735 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
738 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
739 config[no_regs++] = adev->gfx.config.max_gs_threads; in amdgpu_debugfs_gca_config_read()
750 config[no_regs++] = adev->gfx.config.num_gpus; in amdgpu_debugfs_gca_config_read()
752 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; in amdgpu_debugfs_gca_config_read()
754 config[no_regs++] = adev->gfx.config.num_rbs; in amdgpu_debugfs_gca_config_read()
921 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_wave_read()
1015 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gpr_read()
[all …]
A Dsoc15_common.h31 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \
32 adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
36 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \
37 adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
A Damdgpu_amdkfd_gfx_v10_3.c68 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
69 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
127 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
128 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
210 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
211 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
303 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
304 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v10_3()
309 spin_lock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()
[all …]
A Dgfx_v9_4_2.c502 !adev->gfx.compute_ring[1].sched.ready) in gfx_v9_4_2_do_sgprs_init()
516 &adev->gfx.compute_ring[0], in gfx_v9_4_2_do_sgprs_init()
522 adev->gfx.cu_info.number, in gfx_v9_4_2_do_sgprs_init()
541 &adev->gfx.compute_ring[1], in gfx_v9_4_2_do_sgprs_init()
547 adev->gfx.cu_info.number * 2, in gfx_v9_4_2_do_sgprs_init()
581 &adev->gfx.compute_ring[0], in gfx_v9_4_2_do_sgprs_init()
587 adev->gfx.cu_info.number, in gfx_v9_4_2_do_sgprs_init()
645 if (!adev->gfx.compute_ring[0].sched.ready) in gfx_v9_4_2_do_vgprs_init()
659 &adev->gfx.compute_ring[0], in gfx_v9_4_2_do_vgprs_init()
665 adev->gfx.cu_info.number, in gfx_v9_4_2_do_vgprs_init()
[all …]
A Damdgpu_cgs.c173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
191 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
A Damdgpu_amdkfd_gfx_v10.c69 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
70 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
78 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
159 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
160 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
309 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
318 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hiq_mqd_load()
319 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hiq_mqd_load()
324 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
351 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
A Dvcn_v1_0.c336 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
338 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
340 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
342 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
344 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
346 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
348 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
350 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
352 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
354 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
[all …]
A Damdgpu_virt.c68 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait()
525 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
526 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
527 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
528 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
529 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
530 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
531 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
532 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
533 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
A Damdgpu_device.c565 adev->gfx.rlc.funcs && in amdgpu_mm_wreg_mmio_rlc()
2032 adev->gfx.config.num_sc_per_sh = in amdgpu_device_parse_gpu_info_fw()
2034 adev->gfx.config.num_packer_per_sc = in amdgpu_device_parse_gpu_info_fw()
2799 WARN_ON_ONCE(adev->gfx.gfx_off_state); in amdgpu_device_delay_enable_gfx_off()
2803 adev->gfx.gfx_off_state = true; in amdgpu_device_delay_enable_gfx_off()
3454 mutex_init(&adev->gfx.gfx_off_mutex); in amdgpu_device_init()
3494 adev->gfx.gfx_off_req_count = 1; in amdgpu_device_init()
3679 adev->gfx.config.max_shader_engines, in amdgpu_device_init()
3680 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
3681 adev->gfx.config.max_cu_per_sh, in amdgpu_device_init()
[all …]
/linux/Documentation/devicetree/bindings/gpu/
A Daspeed-gfx.txt6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/linux/Documentation/devicetree/bindings/mfd/
A Daspeed-gfx.txt8 - compatible: "aspeed,ast2500-gfx", "syscon"
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/linux/Documentation/devicetree/bindings/pinctrl/
A Daspeed,ast2500-pinctrl.yaml35 0: compatible with "aspeed,ast2500-gfx", "syscon"
85 aspeed,external-nodes = <&gfx>, <&lhc>;
99 gfx: display@1e6e6000 {
100 compatible = "aspeed,ast2500-gfx", "syscon";

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