| /linux/Documentation/devicetree/bindings/arm/mediatek/ |
| A D | mediatek,infracfg.txt | 1 Mediatek infracfg controller
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17 - "mediatek,mt7629-infracfg", "syscon"
18 - "mediatek,mt8135-infracfg", "syscon"
19 - "mediatek,mt8167-infracfg", "syscon"
[all …]
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| A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
47 infracfg: syscon@10001000 {
48 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8183.dtsi | 376 infracfg: syscon@10001000 { label
437 mediatek,infracfg = <&infracfg>;
467 mediatek,infracfg = <&infracfg>;
489 mediatek,infracfg = <&infracfg>;
508 mediatek,infracfg = <&infracfg>;
519 mediatek,infracfg = <&infracfg>;
548 mediatek,infracfg = <&infracfg>;
558 mediatek,infracfg = <&infracfg>;
566 mediatek,infracfg = <&infracfg>;
741 <&infracfg CLK_INFRA_SPI0>;
[all …]
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| A D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
55 mediatek,infracfg = <&infracfg>;
81 mediatek,infracfg = <&infracfg>;
92 mediatek,infracfg = <&infracfg>;
100 mediatek,infracfg = <&infracfg>;
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| A D | mt8516.dtsi | 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
349 <&infracfg CLK_IFR_I2C0_SEL>,
368 <&infracfg CLK_IFR_I2C1_SEL>,
387 <&infracfg CLK_IFR_I2C2_SEL>,
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| A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
205 infracfg: infracfg@10000000 { label
206 compatible = "mediatek,mt7622-infracfg",
217 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
219 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
242 infracfg = <&infracfg>;
251 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
296 clocks = <&infracfg CLK_INFRA_TRNG>;
604 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
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| A D | mt8173.dtsi | 166 clocks = <&infracfg CLK_INFRA_CA53SEL>,
181 clocks = <&infracfg CLK_INFRA_CA53SEL>,
196 clocks = <&infracfg CLK_INFRA_CA72SEL>,
211 clocks = <&infracfg CLK_INFRA_CA72SEL>,
362 infracfg: power-controller@10001000 { label
490 mediatek,infracfg = <&infracfg>;
524 mediatek,infracfg = <&infracfg>;
544 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
552 clocks = <&infracfg CLK_INFRA_CEC>;
580 clocks = <&infracfg CLK_INFRA_M4U>;
[all …]
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| /linux/drivers/soc/mediatek/ |
| A D | mtk-infracfg.c | 27 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
34 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
37 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
39 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
58 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
65 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
67 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
69 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
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| A D | mtk-pm-domains.c | 43 struct regmap *infracfg; member
146 ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_enable()
190 return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_disable()
352 pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg"); in scpsys_add_one_domain()
353 if (IS_ERR(pd->infracfg)) in scpsys_add_one_domain()
354 return ERR_CAST(pd->infracfg); in scpsys_add_one_domain()
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| A D | mtk-scpsys.c | 153 struct regmap *infracfg; member
286 return mtk_infracfg_set_bus_protection(scp->infracfg, in scpsys_bus_protect_enable()
298 return mtk_infracfg_clear_bus_protection(scp->infracfg, in scpsys_bus_protect_disable()
461 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in init_scp()
463 if (IS_ERR(scp->infracfg)) { in init_scp()
465 PTR_ERR(scp->infracfg)); in init_scp()
466 return ERR_CAST(scp->infracfg); in init_scp()
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | mt8192-afe-pcm.yaml | 30 mediatek,infracfg:
32 description: The phandle of the mediatek infracfg controller
63 - mediatek,infracfg
85 mediatek,infracfg = <&infracfg>;
91 <&infracfg CLK_INFRA_AUDIO>,
92 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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| A D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
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| /linux/Documentation/devicetree/bindings/pci/ |
| A D | mediatek-pcie-gen3.yaml | 150 clocks = <&infracfg 44>,
151 <&infracfg 40>,
152 <&infracfg 43>,
153 <&infracfg 97>,
154 <&infracfg 99>,
155 <&infracfg 111>;
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| /linux/drivers/net/wireless/mediatek/mt76/mt7615/ |
| A D | soc.c | 23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| A D | cpufreq-mediatek.txt | 63 clocks = <&infracfg CLK_INFRA_CPUSEL>,
185 clocks = <&infracfg CLK_INFRA_CA53SEL>,
197 clocks = <&infracfg CLK_INFRA_CA53SEL>,
209 clocks = <&infracfg CLK_INFRA_CA72SEL>,
221 clocks = <&infracfg CLK_INFRA_CA72SEL>,
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| /linux/Documentation/devicetree/bindings/soc/mediatek/ |
| A D | scpsys.txt | 32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
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| /linux/Documentation/devicetree/bindings/power/ |
| A D | mediatek,power-controller.yaml | 90 mediatek,infracfg:
141 mediatek,infracfg:
192 mediatek,infracfg:
264 mediatek,infracfg = <&infracfg>;
298 mediatek,infracfg = <&infracfg>;
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| /linux/arch/arm/boot/dts/ |
| A D | mt7629.dtsi | 81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
474 mediatek,infracfg = <&infracfg>;
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| A D | mt7623.dtsi | 80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
236 "mediatek,mt2701-infracfg",
277 infracfg = <&infracfg>;
307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
308 <&infracfg CLK_INFRA_PMICWRAP>;
316 clocks = <&infracfg CLK_INFRA_IRRX>;
[all …]
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| A D | mt8135.dtsi | 133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
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| A D | mt2701.dtsi | 132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
193 clocks = <&infracfg CLK_INFRA_SMI>,
195 <&infracfg CLK_INFRA_SMI>;
223 clocks = <&infracfg CLK_INFRA_M4U>;
435 clocks = <&infracfg CLK_INFRA_AUDIO>,
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| A D | mt7623n.dtsi | 108 clocks = <&infracfg CLK_INFRA_M4U>;
133 clocks = <&infracfg CLK_INFRA_SMI>,
135 <&infracfg CLK_INFRA_SMI>;
264 clocks = <&infracfg CLK_INFRA_CEC>;
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| /linux/Documentation/devicetree/bindings/spi/ |
| A D | spi-slave-mt27xx.txt | 10 It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
29 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | mediatek,ufs-phy.yaml | 63 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
64 <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
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| /linux/include/linux/soc/mediatek/ |
| A D | infracfg.h | 153 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
155 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
|