Searched refs:input_clk (Results 1 – 13 of 13) sorted by relevance
| /linux/drivers/i2c/busses/ |
| A D | i2c-cadence.c | 200 unsigned long input_clk; member
1001 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument
1009 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()
1020 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()
1026 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
1117 unsigned long input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb() local
1122 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); in cdns_i2c_clk_notifier_cb()
1136 id->input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb()
1294 id->input_clk = clk_get_rate(id->clk); in cdns_i2c_probe()
1308 ret = cdns_i2c_setclk(id->input_clk, id); in cdns_i2c_probe()
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | snps,hsdk-pll-clock.txt | 17 input_clk: input-clk {
27 clocks = <&input_clk>;
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| /linux/drivers/gpu/drm/nouveau/ |
| A D | nouveau_led.c | 60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness() local
64 div = input_clk / freq; in nouveau_led_set_brightness()
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| /linux/arch/arc/boot/dts/ |
| A D | hsdk.dts | 62 input_clk: input-clk { label
127 clocks = <&input_clk>;
274 clocks = <&input_clk>;
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| A D | axc003.dtsi | 24 input_clk: input-clk { label
34 clocks = <&input_clk>;
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| A D | axc003_idu.dtsi | 24 input_clk: input-clk { label
34 clocks = <&input_clk>;
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| A D | axc001.dtsi | 31 input_clk: input-clk { label
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| A D | axs10x_mb.dtsi | 70 clocks = <&input_clk>;
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega20_hwmgr.c | 2987 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
2998 input_clk, in vega20_odn_edit_dpm_table()
3009 od_table->GfxclkFmin = input_clk; in vega20_odn_edit_dpm_table()
3011 od_table->GfxclkFmax = input_clk; in vega20_odn_edit_dpm_table()
3030 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
3041 input_clk, in vega20_odn_edit_dpm_table()
3050 od_table->UclkFmax = input_clk; in vega20_odn_edit_dpm_table()
3074 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
3088 input_clk, in vega20_odn_edit_dpm_table()
3106 od_table->GfxclkFreq1 = input_clk; in vega20_odn_edit_dpm_table()
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| A D | vega10_hwmgr.c | 5367 uint32_t input_clk; in vega10_odn_edit_dpm_table() local
5410 input_clk = input[i+1] * 100; in vega10_odn_edit_dpm_table()
5413 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
5414 dpm_table->dpm_levels[input_level].value = input_clk; in vega10_odn_edit_dpm_table()
5415 podn_vdd_dep_table->entries[input_level].clk = input_clk; in vega10_odn_edit_dpm_table()
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| A D | smu7_hwmgr.c | 5437 uint32_t input_clk; in smu7_odn_edit_dpm_table() local
5478 input_clk = input[i+1] * 100; in smu7_odn_edit_dpm_table()
5481 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in smu7_odn_edit_dpm_table()
5482 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
5483 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
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| /linux/drivers/clk/ |
| A D | clk-si5341.c | 75 struct clk *input_clk[SI5341_NUM_INPUTS]; member
1412 m_den = clk_get_rate(data->input_clk[sel]) / 10; in si5341_initialize_pll()
1431 if (!data->input_clk[res]) { in si5341_clk_select_active_input()
1436 if (data->input_clk[i]) { in si5341_clk_select_active_input()
1453 err = clk_prepare_enable(data->input_clk[res]); in si5341_clk_select_active_input()
1580 data->input_clk[i] = input; in si5341_probe()
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| /linux/drivers/media/i2c/ |
| A D | ov5670.c | 2464 u32 input_clk = 0; in ov5670_probe() local
2467 device_property_read_u32(&client->dev, "clock-frequency", &input_clk); in ov5670_probe()
2468 if (input_clk != 19200000) in ov5670_probe()
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