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Searched refs:intel_de_read (Results 1 – 25 of 50) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
A Dintel_fdi.c334 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
345 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
388 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
392 intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
397 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
405 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
435 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
441 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
495 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
505 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
[all …]
A Dintel_combo_phy.c47 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
80 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
93 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
153 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
302 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); in intel_combo_phy_power_up_lanes()
333 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
361 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); in icl_combo_phys_init()
366 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); in icl_combo_phys_init()
370 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); in icl_combo_phys_init()
404 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_uninit()
[all …]
A Dicl_dsi.c276 tmp = intel_de_read(dev_priv, in dsi_program_swing_and_deemphasis()
296 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); in configure_dual_link_mode()
317 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); in configure_dual_link_mode()
442 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
465 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
472 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
602 tmp = intel_de_read(dev_priv, in gen11_dsi_setup_dphy_timings()
611 tmp = intel_de_read(dev_priv, in gen11_dsi_setup_dphy_timings()
818 tmp = intel_de_read(dev_priv, in gen11_dsi_configure_transcoder()
1120 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); in gen11_dsi_config_util_pin()
[all …]
A Dintel_dpll_mgr.c417 val = intel_de_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
588 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
633 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1164 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1240 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1278 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
2041 intel_de_read(dev_priv, in bxt_ddi_pll_get_hw_state()
3321 val = intel_de_read(dev_priv, enable_reg); in mg_pll_get_hw_state()
3459 val = intel_de_read(dev_priv, enable_reg); in icl_pll_get_hw_state()
3676 val = intel_de_read(dev_priv, enable_reg); in icl_pll_power_enable()
[all …]
A Dvlv_dsi.c118 u32 val = intel_de_read(dev_priv, reg); in read_data()
629 val = intel_de_read(dev_priv, port_ctrl); in vlv_dsi_clear_device_ready()
650 temp = intel_de_read(dev_priv, in intel_dsi_port_enable()
672 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
710 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
820 val = intel_de_read(dev_priv, DSPCLK_GATE_D); in intel_dsi_pre_enable()
996 val = intel_de_read(dev_priv, DSPCLK_GATE_D); in intel_dsi_post_disable()
1059 u32 tmp = intel_de_read(dev_priv, in intel_dsi_get_hw_state()
1135 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1138 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
[all …]
A Dintel_backlight.c182 return intel_de_read(dev_priv, in bxt_get_backlight()
377 tmp = intel_de_read(dev_priv, BLC_PWM_CTL2); in i965_disable_backlight()
404 tmp = intel_de_read(dev_priv, in bxt_disable_backlight()
425 tmp = intel_de_read(dev_priv, in cnp_disable_backlight()
577 ctl = intel_de_read(dev_priv, BLC_PWM_CTL); in i9xx_enable_backlight()
700 pwm_ctl = intel_de_read(dev_priv, in bxt_enable_backlight()
736 pwm_ctl = intel_de_read(dev_priv, in cnp_enable_backlight()
1314 ctl = intel_de_read(dev_priv, BLC_PWM_CTL); in i9xx_setup_backlight()
1356 ctl = intel_de_read(dev_priv, BLC_PWM_CTL); in i965_setup_backlight()
1412 pwm_ctl = intel_de_read(dev_priv, in bxt_setup_backlight()
[all …]
A Dintel_audio.c306 tmp = intel_de_read(dev_priv, reg_eldv); in intel_eld_uptodate()
312 tmp = intel_de_read(dev_priv, reg_elda); in intel_eld_uptodate()
332 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_disable()
339 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
593 val = intel_de_read(i915, AUD_CONFIG_BE); in enable_audio_dsc_wa()
716 tmp = intel_de_read(dev_priv, aud_config); in ilk_audio_codec_disable()
728 tmp = intel_de_read(dev_priv, aud_cntrl_st2); in ilk_audio_codec_disable()
783 tmp = intel_de_read(dev_priv, aud_cntrl_st2); in ilk_audio_codec_enable()
788 tmp = intel_de_read(dev_priv, aud_cntl_st); in ilk_audio_codec_enable()
799 tmp = intel_de_read(dev_priv, aud_cntrl_st2); in ilk_audio_codec_enable()
[all …]
A Dintel_pps.c474 intel_de_read(dev_priv, pp_stat_reg), in wait_panel_status()
475 intel_de_read(dev_priv, pp_ctrl_reg)); in wait_panel_status()
481 intel_de_read(dev_priv, pp_stat_reg), in wait_panel_status()
482 intel_de_read(dev_priv, pp_ctrl_reg)); in wait_panel_status()
612 intel_de_read(dev_priv, pp_stat_reg), in intel_pps_vdd_on_unlocked()
613 intel_de_read(dev_priv, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
680 intel_de_read(dev_priv, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
681 intel_de_read(dev_priv, pp_ctrl_reg)); in intel_pps_vdd_off_sync_unlocked()
1340 intel_de_read(dev_priv, regs.pp_on), in pps_init_registers()
1341 intel_de_read(dev_priv, regs.pp_off), in pps_init_registers()
[all …]
A Dintel_dpio_phy.c332 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
390 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
411 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)); in _bxt_ddi_phy_init()
416 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)); in _bxt_ddi_phy_init()
450 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)); in _bxt_ddi_phy_init()
458 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); in _bxt_ddi_phy_init()
470 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); in bxt_ddi_phy_uninit()
474 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in bxt_ddi_phy_uninit()
514 val = intel_de_read(dev_priv, reg); in __phy_reg_verify_state()
617 u32 val = intel_de_read(dev_priv, in bxt_ddi_phy_set_lane_optim_mask()
[all …]
A Dintel_ddi.c745 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
786 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
1259 val = intel_de_read(dev_priv, in icl_mg_phy_set_signal_levels()
1265 val = intel_de_read(dev_priv, in icl_mg_phy_set_signal_levels()
1436 return !(intel_de_read(i915, reg) & clk_off); in _icl_ddi_is_clock_enabled()
1683 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in jsl_ddi_tc_is_clock_enabled()
1736 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in icl_ddi_tc_is_clock_enabled()
1741 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); in icl_ddi_tc_is_clock_enabled()
1852 tmp = intel_de_read(i915, DPLL_CTRL2); in skl_ddi_get_pll()
2740 val = intel_de_read(dev_priv, in intel_ddi_post_disable_dp()
[all …]
A Dintel_lvds.c91 val = intel_de_read(dev_priv, lvds_reg); in intel_lvds_port_enabled()
131 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
149 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in intel_lvds_get_config()
164 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
169 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
173 val = intel_de_read(dev_priv, PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
210 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
322 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
341 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); in intel_disable_lvds()
810 val = intel_de_read(dev_priv, lvds_encoder->reg); in compute_is_dual_link_lvds()
[all …]
A Dvlv_dsi_pll.c205 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
219 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
244 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
332 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
350 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
420 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
531 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
554 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
561 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
565 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
A Dintel_display_power.c448 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enable()
477 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_disable()
494 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_enable()
530 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_disable()
782 v = intel_de_read(dev_priv, DC_STATE_EN); in gen9_write_dc_state()
875 val = intel_de_read(dev_priv, DC_STATE_EN); in gen9_set_dc_state()
929 val = intel_de_read(dev_priv, DC_STATE_EN); in tgl_disable_dc3co()
968 !intel_de_read(dev_priv, in assert_dmc_loaded()
5397 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
5442 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
[all …]
A Dintel_display.c582 val = intel_de_read(dev_priv, reg); in ilk_enable_pch_transcoder()
595 val = intel_de_read(dev_priv, reg); in ilk_enable_pch_transcoder()
678 val = intel_de_read(dev_priv, reg); in ilk_disable_pch_transcoder()
689 val = intel_de_read(dev_priv, reg); in ilk_disable_pch_transcoder()
763 val = intel_de_read(dev_priv, reg); in intel_enable_transcoder()
802 val = intel_de_read(dev_priv, reg); in intel_disable_transcoder()
1642 temp = intel_de_read(dev_priv, reg); in ilk_pch_enable()
2586 val = intel_de_read(dev_priv, reg); in hsw_set_frame_start_delay()
5389 tmp = intel_de_read(dev_priv, in hsw_get_ddi_port_state()
5464 u32 tmp = intel_de_read(dev_priv, in hsw_get_pipe_config()
[all …]
A Dintel_fifo_underrun.c99 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
126 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
149 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
180 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
236 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
269 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
418 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & in intel_cpu_fifo_underrun_irq_handler()
A Dintel_dvo.c141 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
156 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
172 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
195 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
199 intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
210 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
217 intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
301 dvo_val = intel_de_read(dev_priv, dvo_reg) & in intel_dvo_pre_enable()
499 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
A Dg4x_dp.c158 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); in intel_dp_prepare()
273 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
297 val = intel_de_read(dev_priv, dp_reg); in g4x_dp_port_enabled()
349 tmp = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_get_config()
354 u32 trans_dp = intel_de_read(dev_priv, in intel_dp_get_config()
431 (intel_de_read(dev_priv, intel_dp->output_reg) & in intel_dp_link_down()
664 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); in intel_enable_dp()
1201 return intel_de_read(dev_priv, SDEISR) & bit; in ibx_digital_port_connected()
1224 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; in g4x_digital_port_connected()
1247 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; in gm45_digital_port_connected()
[all …]
A Dintel_tv.c910 u32 tmp = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_hw_state()
1099 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_config()
1100 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); in intel_tv_get_config()
1101 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); in intel_tv_get_config()
1102 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); in intel_tv_get_config()
1103 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); in intel_tv_get_config()
1138 tmp = intel_de_read(dev_priv, TV_WIN_POS); in intel_tv_get_config()
1142 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); in intel_tv_get_config()
1440 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_pre_enable()
1624 tv_dac = intel_de_read(dev_priv, TV_DAC); in intel_tv_detect_type()
[all …]
A Dintel_crt.c81 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
118 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
466 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
490 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
525 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
541 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
592 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
741 u32 vsync = intel_de_read(dev_priv, vsync_reg); in intel_crt_load_detect()
958 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
1009 adpa = intel_de_read(dev_priv, adpa_reg); in intel_crt_init()
[all …]
A Dintel_hdmi.c275 u32 val = intel_de_read(dev_priv, reg); in ibx_write_infoframe()
332 u32 val = intel_de_read(dev_priv, reg); in ibx_infoframes_enabled()
354 u32 val = intel_de_read(dev_priv, reg); in cpt_write_infoframe()
432 u32 val = intel_de_read(dev_priv, reg); in vlv_write_infoframe()
481 *data++ = intel_de_read(dev_priv, in vlv_read_infoframe()
555 *data++ = intel_de_read(dev_priv, in hsw_read_infoframe()
563 u32 val = intel_de_read(dev_priv, in hsw_infoframes_enabled()
862 u32 val = intel_de_read(dev_priv, reg); in g4x_set_infoframes()
1047 u32 val = intel_de_read(dev_priv, reg); in ibx_set_infoframes()
1105 u32 val = intel_de_read(dev_priv, reg); in cpt_set_infoframes()
[all …]
A Dintel_overlay.c328 tmp = intel_de_read(dev_priv, DOVSTA); in intel_overlay_continue()
947 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
949 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1285 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); in intel_overlay_attrs_ioctl()
1286 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); in intel_overlay_attrs_ioctl()
1287 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); in intel_overlay_attrs_ioctl()
1288 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); in intel_overlay_attrs_ioctl()
1289 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); in intel_overlay_attrs_ioctl()
1290 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); in intel_overlay_attrs_ioctl()
1465 error->dovsta = intel_de_read(dev_priv, DOVSTA); in intel_overlay_capture_error_state()
[all …]
A Dintel_vrr.c216 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); in intel_vrr_get_config()
229 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; in intel_vrr_get_config()
230 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; in intel_vrr_get_config()
231 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; in intel_vrr_get_config()
A Dintel_cdclk.c277 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
452 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
736 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
785 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
874 val = intel_de_read(dev_priv, LCPLL1_CTL); in skl_dpll0_update()
881 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_dpll0_update()
919 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_get_cdclk()
1096 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1158 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_sanitize_cdclk()
1430 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
[all …]
A Dintel_display_debugfs.c72 mask = intel_de_read(dev_priv, FBC_STATUS) & in i915_fbc_status()
304 val = intel_de_read(dev_priv, in psr_source_status()
321 val = intel_de_read(dev_priv, in psr_source_status()
366 val = intel_de_read(dev_priv, in intel_psr_status()
370 val = intel_de_read(dev_priv, in intel_psr_status()
384 val = intel_de_read(dev_priv, in intel_psr_status()
405 val = intel_de_read(dev_priv, in intel_psr_status()
575 intel_de_read(dev_priv, DMC_DEBUG3)); in i915_dmc_info()
584 intel_de_read(dev_priv, dc5_reg)); in i915_dmc_info()
587 intel_de_read(dev_priv, dc6_reg)); in i915_dmc_info()
[all …]
/linux/drivers/gpu/drm/i915/
A Di915_suspend.c43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()

Completed in 761 milliseconds

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