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Searched refs:ip_versions (Results 1 – 25 of 32) sorted by relevance

12

/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_discovery.c626 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
661 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gmc_ip_blocks()
736 adev->ip_versions[MP0_HWIP][0]); in amdgpu_discovery_set_psp_ip_blocks()
777 adev->ip_versions[MP1_HWIP][0]); in amdgpu_discovery_set_smu_ip_blocks()
807 adev->ip_versions[DCE_HWIP][0]); in amdgpu_discovery_set_display_ip_blocks()
820 adev->ip_versions[DCI_HWIP][0]); in amdgpu_discovery_set_display_ip_blocks()
856 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gc_ip_blocks()
892 adev->ip_versions[SDMA0_HWIP][0]); in amdgpu_discovery_set_sdma_ip_blocks()
911 adev->ip_versions[UVD_HWIP][0]); in amdgpu_discovery_set_mm_ip_blocks()
924 adev->ip_versions[VCE_HWIP][0]); in amdgpu_discovery_set_mm_ip_blocks()
[all …]
A Dhdp_v4_0.c52 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0)) in hdp_v4_0_invalidate_hdp()
82 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
94 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
95 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
96 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
97 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
139 switch (adev->ip_versions[HDP_HWIP][0]) { in hdp_v4_0_init_registers()
A Dgmc_v9_0.c582 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
600 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_process_interrupt()
699 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) in gmc_v9_0_use_invalidate_semaphore()
1113 switch (adev->ip_versions[DCE_HWIP][0]) { in gmc_v9_0_get_vbios_fb_size()
1154 switch (adev->ip_versions[UMC_HWIP][0]) { in gmc_v9_0_set_umc_funcs()
1193 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_set_mmhub_funcs()
1208 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_set_mmhub_ras_funcs()
1237 switch (adev->ip_versions[UMC_HWIP][0]) { in gmc_v9_0_set_mca_funcs()
1399 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_mc_init()
1515 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_sw_init()
[all …]
A Dmmhub_v2_0.c156 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
605 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
631 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_light_sleep()
648 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_light_sleep()
667 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_set_clockgating()
692 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_get_clockgating()
A Dsoc15.c159 if (adev->ip_versions[VCE_HWIP][0]) { in soc15_query_video_codecs()
160 switch (adev->ip_versions[VCE_HWIP][0]) { in soc15_query_video_codecs()
172 switch (adev->ip_versions[UVD_HWIP][0]) { in soc15_query_video_codecs()
344 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
345 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) in soc15_get_xclk()
347 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
348 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
579 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_asic_reset_method()
644 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_supports_baco()
998 switch (adev->ip_versions[GC_HWIP][0]) { in soc15_common_early_init()
[all …]
A Dgmc_v10_0.c136 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
271 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
660 switch (adev->ip_versions[UMC_HWIP][0]) { in gmc_v10_0_set_umc_funcs()
677 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v10_0_set_mmhub_funcs()
690 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
860 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
1136 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) in gmc_v10_0_set_clockgating_state()
1148 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) in gmc_v10_0_get_clockgating_state()
A Dsdma_v4_0.c472 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_golden_registers()
542 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_setup_ulv()
593 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || in sdma_v4_0_destroy_inst_ctx()
594 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) in sdma_v4_0_destroy_inst_ctx()
624 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_microcode()
1398 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_pg()
1841 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_fw_support_paging_queue()
2139 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0)) in sdma_v4_0_process_trap_irq()
2146 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0)) in sdma_v4_0_process_trap_irq()
2362 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_set_powergating_state()
[all …]
A Damdgpu_psp.c78 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_check_pmfw_centralized_cstate_management()
101 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_early_init()
283 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) { in psp_sw_init()
326 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || in psp_sw_init()
327 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { in psp_sw_init()
357 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || in psp_sw_fini()
358 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) in psp_sw_fini()
617 switch (psp->adev->ip_versions[MP0_HWIP][0]) { in psp_skip_tmr()
1014 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || in psp_xgmi_terminate()
1015 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && in psp_xgmi_terminate()
[all …]
A Dgfx_v9_0.c961 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
1209 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1320 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1674 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_microcode()
1975 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_rlc_init()
2155 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_gpu_early_init()
2319 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_sw_init()
2613 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_sq_config()
3174 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_rlc_resume()
4249 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_get_gpu_clock_counter()
[all …]
A Dathub_v2_0.c80 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v2_0_set_clockgating()
A Dathub_v2_1.c73 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v2_1_set_clockgating()
A Dpsp_v13_0.c50 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_init_microcode()
61 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_init_microcode()
A Dnv.c183 switch (adev->ip_versions[UVD_HWIP][0]) { in nv_query_video_codecs()
514 switch (adev->ip_versions[MP1_HWIP][0]) { in nv_asic_reset_method()
762 switch (adev->ip_versions[GC_HWIP][0]) { in nv_common_early_init()
1093 switch (adev->ip_versions[NBIO_HWIP][0]) { in nv_common_set_clockgating_state()
A Dgfx_v10_0.c3711 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_spm_golden_registers()
3734 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_golden_registers()
3966 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_fw_write_wait()
4047 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_gfxoff_flag()
4074 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_microcode()
4665 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_gpu_early_init()
4799 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_sw_init()
6318 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_cp_gfx_set_doorbell()
6567 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_kiq_setting()
7284 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_grbm_cam_remapping()
[all …]
A Dsdma_v5_2.c139 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_init_microcode()
177 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) in sdma_v5_2_init_microcode()
1541 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_clock_gating()
1578 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_light_sleep()
1607 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_set_clockgating_state()
A Dgfxhub_v2_1.c508 switch (adev->ip_versions[XGMI_HWIP][0]) { in gfxhub_v2_1_get_xgmi_info()
546 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) { in gfxhub_v2_1_utcl2_harvest()
A Dnavi10_ih.c110 if (adev->ip_versions[OSSSYS_HWIP][0] < IP_VERSION(5, 0, 3)) in force_update_wptr_for_self_int()
333 switch (adev->ip_versions[OSSSYS_HWIP][0]) { in navi10_ih_irq_init()
A Dpsp_v11_0.c96 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v11_0_init_microcode()
132 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v11_0_init_microcode()
A Dsdma_v5_0.c190 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_golden_registers()
251 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) in sdma_v5_0_init_microcode()
256 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_microcode()
1637 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_set_clockgating_state()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c93 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
94 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
97 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_init_microcode()
124 adev->ip_versions[MP1_HWIP][0]); in smu_v11_0_init_microcode()
242 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_check_fw_version()
275 adev->ip_versions[MP1_HWIP][0]); in smu_v11_0_check_fw_version()
756 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) || in smu_v11_0_init_display_count()
757 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
759 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1150 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_gfx_off_control()
[all …]
A Dnavi10_ppt.c348 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
357 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
928 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_smu_metrics_data()
938 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || in navi1x_get_smu_metrics_data()
1515 switch (adev->ip_versions[MP1_HWIP][0]) { in navi10_populate_umd_state_clk()
2568 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || in navi10_need_umc_cdr_workaround()
2569 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) in navi10_need_umc_cdr_workaround()
2697 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) in navi10_run_umc_cdr_workaround()
2703 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) in navi10_run_umc_cdr_workaround()
3157 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_gpu_metrics()
[all …]
A Dsienna_cichlid_ppt.c77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
85 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in get_table_size()
301 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_allowed_feature_mask()
499 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_throttler_status_locked()
520 bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_smu_metrics_data()
1126 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_print_clk_levels()
1893 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_dump_od_table()
2117 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_od_edit_dpm_table()
2821 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) { in sienna_cichlid_dump_pptable()
3581 bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_gpu_metrics()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c462 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) in is_support_sw_smu()
582 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_set_funcs()
703 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || in smu_late_init()
704 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) in smu_late_init()
1150 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_smc_hw_setup()
1301 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { in smu_start_smc_engine()
1426 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
1448 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_disable_dpms()
1477 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && in smu_disable_dpms()
2311 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_get_power_limit()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c92 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_init_microcode()
98 adev->ip_versions[MP1_HWIP][0]); in smu_v13_0_init_microcode()
217 switch (smu->adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_check_fw_version()
227 smu->adev->ip_versions[MP1_HWIP][0]); in smu_v13_0_check_fw_version()
749 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v13_0_gfx_off_control()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c1421 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_init()
1751 switch (adev->ip_versions[DCE_HWIP][0]) { in load_dmcu_fw()
1844 switch (adev->ip_versions[DCE_HWIP][0]) { in dm_dmub_sw_init()
2173 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_smu_write_watermarks_table()
4205 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_initialize_drm_device()
4217 adev->ip_versions[DCE_HWIP][0]); in amdgpu_dm_initialize_drm_device()
4222 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_initialize_drm_device()
4320 switch (adev->ip_versions[DCE_HWIP][0]) { in amdgpu_dm_initialize_drm_device()
4340 adev->ip_versions[DCE_HWIP][0]); in amdgpu_dm_initialize_drm_device()
4493 switch (adev->ip_versions[DCE_HWIP][0]) { in dm_early_init()
[all …]

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