Searched refs:lane_width (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | hwmgr_ppt.h | 97 uint8_t lane_width; member
|
| A D | vega20_hwmgr.c | 3367 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3461 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3468 (lane_width == 1) ? "x1" : in vega20_print_clock_levels()
3469 (lane_width == 2) ? "x2" : in vega20_print_clock_levels()
3470 (lane_width == 3) ? "x4" : in vega20_print_clock_levels()
3471 (lane_width == 4) ? "x8" : in vega20_print_clock_levels()
3472 (lane_width == 5) ? "x12" : in vega20_print_clock_levels()
3473 (lane_width == 6) ? "x16" : "", in vega20_print_clock_levels()
3476 (current_lane_width == lane_width) ? in vega20_print_clock_levels()
|
| A D | vega10_hwmgr.c | 1275 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
4637 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_print_clock_levels() local
4701 lane_width = pptable->PcieLaneCount[i]; in vega10_print_clock_levels()
4708 (lane_width == 1) ? "x1" : in vega10_print_clock_levels()
4709 (lane_width == 2) ? "x2" : in vega10_print_clock_levels()
4710 (lane_width == 3) ? "x4" : in vega10_print_clock_levels()
4711 (lane_width == 4) ? "x8" : in vega10_print_clock_levels()
4712 (lane_width == 5) ? "x12" : in vega10_print_clock_levels()
4713 (lane_width == 6) ? "x16" : "", in vega10_print_clock_levels()
4715 (current_lane_width == lane_width) ? in vega10_print_clock_levels()
|
| A D | process_pptables_v1_0.c | 519 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
557 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
|
| A D | vega10_processpptables.c | 816 pcie_table->entries[i].lane_width = in get_pcie_table()
|
| A D | smu7_hwmgr.c | 678 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
|
| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | arcturus_ppt.c | 786 uint32_t gen_speed, lane_width; in arcturus_print_clk_levels() local
942 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in arcturus_print_clk_levels()
948 (lane_width == 1) ? "x1" : in arcturus_print_clk_levels()
949 (lane_width == 2) ? "x2" : in arcturus_print_clk_levels()
950 (lane_width == 3) ? "x4" : in arcturus_print_clk_levels()
951 (lane_width == 4) ? "x8" : in arcturus_print_clk_levels()
952 (lane_width == 5) ? "x12" : in arcturus_print_clk_levels()
953 (lane_width == 6) ? "x16" : "", in arcturus_print_clk_levels()
|
| A D | navi10_ppt.c | 1273 uint32_t gen_speed, lane_width; in navi10_print_clk_levels() local
1337 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_print_clk_levels()
1352 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_print_clk_levels()
|
| A D | sienna_cichlid_ppt.c | 1010 uint32_t gen_speed, lane_width; in sienna_cichlid_print_clk_levels() local
1076 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in sienna_cichlid_print_clk_levels()
1092 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in sienna_cichlid_print_clk_levels()
|
| /linux/drivers/gpu/drm/radeon/ |
| A D | si_dpm.c | 4681 u32 lane_width; in si_init_smc_table() local
4752 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4753 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5898 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5906 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5907 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
|
| /linux/drivers/gpu/drm/amd/pm/powerplay/ |
| A D | si_dpm.c | 5143 u32 lane_width; in si_init_smc_table() local
5214 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5215 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6355 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6363 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6364 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
|
Completed in 77 milliseconds