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Searched refs:mask_sh (Results 1 – 25 of 90) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hubp.h33 #define HUBP_MASK_SH_LIST_DCN31(mask_sh)\ argument
41 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
42 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
46 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
48 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
49 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
50 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
53 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
54 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
177 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
A Ddcn31_optc.h119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
132 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
136 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
191 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
205 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
207 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
A Ddcn31_dio_link_encoder.h42 #define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \ argument
43 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
44 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
45 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
46 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
47 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
62 LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
63 LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
64 LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
96 #define DPCS_DCN31_MASK_SH_LIST(mask_sh)\ argument
[all …]
A Ddcn31_hubbub.h54 #define HUBBUB_MASK_SH_LIST_DCN31(mask_sh)\ argument
55 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
56 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
60 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
61 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
62 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
63 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
64 HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\
91 HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
93 HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
[all …]
A Ddcn31_dccg.h73 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \ argument
82 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
102 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
103 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
104 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
105 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
108 DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
109 DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
135 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
136 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hubp.h37 #define HUBP_MASK_SH_LIST_DCN30_BASE(mask_sh)\ argument
38 HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
47 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh)
50 #define HUBP_MASK_SH_LIST_DCN30(mask_sh)\ argument
58 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
63 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
64 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
65 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
69 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
193 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
A Ddcn30_mmhubbub.h142 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \ argument
241 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
278 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ argument
300 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
307 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
315 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
322 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
330 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
337 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
345 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
[all …]
A Ddcn30_optc.h128 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
134 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
141 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
145 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
178 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
207 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
208 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
209 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
221 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
241 OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
[all …]
A Ddcn30_dio_stream_encoder.h113 #define SE_COMMON_MASK_SH_LIST_DCN30_BASE(mask_sh)\ argument
127 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
146 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
147 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
148 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
159 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
193 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
206 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
253 SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
272 #define SE_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ argument
[all …]
A Ddcn30_mpc.h291 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
316 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
322 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
323 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
398 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
424 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
430 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
431 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
589 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
[all …]
A Ddcn30_dpp.h177 #define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\ argument
179 TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
181 TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
259 TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
264 TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
265 TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
310 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
381 #define DPP_REG_LIST_SH_MASK_DCN30(mask_sh)\ argument
382 DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \
383 TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
[all …]
A Ddcn30_dwb.h155 #define DWBC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ argument
166 SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_EYE_SELECTION, mask_sh),\
168 SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_NEW_CONTENT, mask_sh),\
179 SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_EN, mask_sh),\
180 SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_CONT_EN, mask_sh),\
181 SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_SRC_SEL, mask_sh),\
190 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_FORMAT, mask_sh),\
191 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_DENORM, mask_sh),\
192 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MAX, mask_sh),\
193 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MIN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp.h186 #define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\ argument
209 #define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\ argument
210 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
368 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
369 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \
371 TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \
545 #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ argument
546 TF_REG_LIST_SH_MASK_DCN(mask_sh), \
547 TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
548 TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
[all …]
A Ddcn20_link_encoder.h35 #define UNIPHY_MASK_SH_LIST(mask_sh)\ argument
43 #define DPCS_MASK_SH_LIST(mask_sh)\ argument
152 #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\ argument
153 DPCS_MASK_SH_LIST(mask_sh),\
174 #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\ argument
175 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
176 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
179 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
183 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
184 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
[all …]
A Ddcn20_dsc.h93 #define DSC_REG_LIST_SH_MASK_DCN20(mask_sh)\ argument
135 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
136 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
137 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
139 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
140 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
141 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
142 DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
143 DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
144 DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
[all …]
A Ddcn20_mmhubbub.h97 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ argument
104 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
114 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
133 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
153 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
161 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
173 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
254 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_aux.h93 #define DCE10_AUX_MASK_SH_LIST(mask_sh)\ argument
94 AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
100 AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
104 AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
115 #define DCE_AUX_MASK_SH_LIST(mask_sh)\ argument
116 AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
117 AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
128 AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
139 #define DCE12_AUX_MASK_SH_LIST(mask_sh)\ argument
165 #define DCN10_AUX_MASK_SH_LIST(mask_sh)\ argument
[all …]
A Ddce_opp.h121 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
130 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
134 #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ argument
135 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
140 #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ argument
146 #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ argument
157 #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ argument
158 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
160 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ argument
206 #define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\ argument
[all …]
A Ddce_transform.h190 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
191 XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
221 XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
252 XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
254 #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \ argument
267 XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
270 #define XFM_COMMON_MASK_SH_LIST_DCE60(mask_sh) \ argument
284 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
285 XFM_SF(DATA_FORMAT, INTERLEAVE_EN, mask_sh), \
391 XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
[all …]
A Ddce_stream_encoder.h146 SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
166 SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
167 SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
168 SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
196 SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
248 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
249 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
291 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ argument
292 SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
319 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
[all …]
A Ddce_ipp.h69 IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
70 IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
77 IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
79 IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
82 IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
83 IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
84 IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
153 IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
154 IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
167 IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
[all …]
A Ddce_hwseq.h727 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
732 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
740 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
750 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
762 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
812 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
871 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
911 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
924 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
967 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
[all …]
A Ddce_mem_input.h262 MI_DMIF_PG_MASK_SH_DCE6(mask_sh, ),\
263 MI_GFX6_TILE_MASK_SH_LIST(mask_sh, )
286 MI_DCP_MASK_SH_LIST(mask_sh, ),\
287 MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\
288 MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\
289 MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
292 MI_DCE8_MASK_SH_LIST(mask_sh),\
296 MI_DCE11_2_MASK_SH_LIST(mask_sh),\
297 MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
325 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubbub.h55 #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ argument
82 HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
101 #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ argument
102 HUBBUB_MASK_SH_LIST_HVM(mask_sh), \
103 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
104 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
107 HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
108 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
109 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
110 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
[all …]
A Ddcn21_hubp.h44 #define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\ argument
45 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
46 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
58 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
59 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
71 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
74 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
81 HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
100 #define HUBP_MASK_SH_LIST_DCN21(mask_sh)\ argument
[all …]

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