Home
last modified time | relevance | path

Searched refs:memory_clock (Results 1 – 25 of 26) sorted by relevance

12

/linux/drivers/gpu/drm/radeon/
A Drv740_dpm.c93 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
104 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
186 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
204 memory_clock, false, &dividers); in rv740_populate_mclk_value()
246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
265 memory_clock); in rv740_populate_mclk_value()
270 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
404 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
408 if ((memory_clock < 10000) || (memory_clock > 47500)) in rv740_get_mclk_frequency_ratio()
411 mc_para_index = (u8)((memory_clock - 10000) / 2500); in rv740_get_mclk_frequency_ratio()
A Drv770_dpm.h184 u32 engine_clock, u32 memory_clock,
205 u32 engine_clock, u32 memory_clock,
212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
A Dcypress_dpm.c573 memory_clock); in cypress_populate_mclk_value()
610 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio() argument
616 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
618 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
623 if (memory_clock < 65000) in cypress_get_mclk_frequency_ratio()
625 else if (memory_clock > 135000) in cypress_get_mclk_frequency_ratio()
632 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
634 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
639 if (memory_clock < 40000) in cypress_get_mclk_frequency_ratio()
641 else if (memory_clock > 115000) in cypress_get_mclk_frequency_ratio()
[all …]
A Dcypress_dpm.h125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
A Dsi_dpm.h237 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
238 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
A Drv730_dpm.c117 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
133 memory_clock, false, &dividers); in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
A Dci_dpm.c2460 const u32 memory_clock, in ci_register_patching_mc_arb() argument
2472 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2476 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2752 u32 memory_clock, in ci_calculate_mclk_params() argument
2824 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
2839 u32 memory_clock, in ci_populate_single_memory_level() argument
2849 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
2857 memory_clock, &memory_level->MinVddci); in ci_populate_single_memory_level()
2865 memory_clock, &memory_level->MinMvdd); in ci_populate_single_memory_level()
2875 memory_clock, in ci_populate_single_memory_level()
[all …]
A Drv770_dpm.c319 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, in rv770_calculate_fractional_mpll_feedback_divider() argument
330 fyclk = (memory_clock * 8) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
332 fyclk = (memory_clock * 4) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
388 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
412 memory_clock, false, &dividers); in rv770_populate_mclk_value()
419 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, in rv770_populate_mclk_value()
446 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, in rv770_populate_mclk_value()
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
A Dsi_dpm.c3804 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
3808 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
3810 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
3822 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
3824 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
3829 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
3831 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
4856 u32 memory_clock, in si_populate_mclk_value() argument
4902 freq_nom = memory_clock * 4; in si_populate_mclk_value()
4904 freq_nom = memory_clock * 2; in si_populate_mclk_value()
[all …]
A Dni_dpm.c2162 u32 memory_clock, in ni_populate_mclk_value() argument
2184 memory_clock, strobe_mode, &dividers); in ni_populate_mclk_value()
2238 u32 vco_freq = memory_clock * dividers.post_div; in ni_populate_mclk_value()
2257 memory_clock); in ni_populate_mclk_value()
2281 mclk->mclk_value = cpu_to_be32(memory_clock); in ni_populate_mclk_value()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Diceland_smumgr.c1046 uint32_t memory_clock, in iceland_calculate_mclk_params() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 65000) { in iceland_get_mclk_frequency_ratio()
1199 if (memory_clock < 10000) { in iceland_get_ddr3_mclk_frequency_ratio()
1229 uint32_t memory_clock, in iceland_populate_single_memory_level() argument
1252 memory_clock, in iceland_populate_single_memory_level()
1585 uint32_t memory_clock, in iceland_populate_memory_timing_parameters() argument
1595 engine_clock, memory_clock); in iceland_populate_memory_timing_parameters()
1729 const uint32_t memory_clock, in iceland_convert_mc_reg_table_entry_to_smc() argument
[all …]
A Dci_smumgr.c1024 uint32_t memory_clock, in ci_calculate_mclk_params() argument
1124 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1126 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1131 if (memory_clock < 65000) in ci_get_mclk_frequency_ratio()
1146 if (memory_clock < 10000) in ci_get_ddr3_mclk_frequency_ratio()
1175 uint32_t memory_clock, in ci_populate_single_memory_level() argument
1196 memory_clock, in ci_populate_single_memory_level()
1205 memory_clock, in ci_populate_single_memory_level()
1623 uint32_t memory_clock, in ci_populate_memory_timing_parameters() argument
1763 const uint32_t memory_clock, in ci_convert_mc_reg_table_entry_to_smc() argument
[all …]
A Dtonga_smumgr.c789 uint32_t memory_clock, in tonga_calculate_mclk_params() argument
926 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
928 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
933 if (memory_clock < 65000) in tonga_get_mclk_frequency_ratio()
948 if (memory_clock < 10000) in tonga_get_ddr3_mclk_frequency_ratio()
950 else if (memory_clock >= 80000) in tonga_get_ddr3_mclk_frequency_ratio()
961 uint32_t memory_clock, in tonga_populate_single_memory_level() argument
985 memory_clock, in tonga_populate_single_memory_level()
1460 uint32_t memory_clock, in tonga_populate_memory_timing_parameters() argument
2108 const uint32_t memory_clock, in tonga_convert_mc_reg_table_entry_to_smc() argument
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dppatomctrl.h301 …t_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_in…
305 …et_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
324 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
A Dsmu7_hwmgr.c3363 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3428 if (smu7_ps->performance_levels[1].memory_clock < in smu7_apply_state_adjust_rules()
3429 smu7_ps->performance_levels[0].memory_clock) in smu7_apply_state_adjust_rules()
3430 smu7_ps->performance_levels[1].memory_clock = in smu7_apply_state_adjust_rules()
3431 smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3759 uint32_t engine_clock, memory_clock; in smu7_get_pp_table_entry_callback_func_v0() local
3766 data->highest_mclk = memory_clock; in smu7_get_pp_table_entry_callback_func_v0()
3783 performance_level->memory_clock = memory_clock; in smu7_get_pp_table_entry_callback_func_v0()
4276 smu7_ps->performance_levels[0].memory_clock, in smu7_trim_dpm_states()
4649 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()
[all …]
A Dhardwaremanager.c399 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
409 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
A Dppatomctrl.c212 uint32_t memory_clock) in atomctrl_set_engine_dram_timings_rv770() argument
225 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); in atomctrl_set_engine_dram_timings_rv770()
1322 const uint32_t memory_clock, in atomctrl_get_memory_clock_spread_spectrum() argument
1326 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); in atomctrl_get_memory_clock_spread_spectrum()
1368 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, in atomctrl_set_ac_timing_ai() argument
1376 memory_clock & SET_CLOCK_FREQ_MASK; in atomctrl_set_ac_timing_ai()
A Dsmu7_hwmgr.h55 uint32_t memory_clock; member
A Dsmu10_hwmgr.c1108 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; in smu10_get_performance_level()
1111 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ in smu10_get_performance_level()
A Dsmu8_hwmgr.c1612 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; in smu8_get_performance_level()
1614 level->memory_clock = data->sys_info.nbp_memory_clock[0]; in smu8_get_performance_level()
/linux/drivers/gpu/drm/amd/pm/inc/
A Damdgpu_smu.h272 uint32_t memory_clock; member
405 uint32_t memory_clock; member
A Dhardwaremanager.h273 uint32_t memory_clock; member
/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dsi_dpm.c4273 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
4275 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
4287 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
4289 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
4292 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
4294 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
4296 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
5318 u32 memory_clock, in si_populate_mclk_value() argument
5364 freq_nom = memory_clock * 4; in si_populate_mclk_value()
5366 freq_nom = memory_clock * 2; in si_populate_mclk_value()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dnavi10_ppt.c1897 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
1921 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
A Dsienna_cichlid_ppt.c1529 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1553 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()

Completed in 150 milliseconds

12