Home
last modified time | relevance | path

Searched refs:optc1 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_optc.c32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
110 if (h_blank < optc1->min_h_blank) in optc201_validate_timing()
117 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; in optc201_validate_timing()
195 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
196 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
198 optc1->min_h_blank = 32; in dcn201_timing_generator_init()
199 optc1->min_v_blank = 3; in dcn201_timing_generator_init()
201 optc1->min_h_sync_width = 8; in dcn201_timing_generator_init()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_optc.c31 optc1->tg_regs->reg
34 optc1->base.ctx
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
216 optc1->opp_count = 1; in optc2_set_odm_bypass()
257 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
599 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
600 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
602 optc1->min_h_blank = 32; in dcn20_timing_generator_init()
603 optc1->min_v_blank = 3; in dcn20_timing_generator_init()
604 optc1->min_v_blank_interlace = 5; in dcn20_timing_generator_init()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_optc.c32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
177 optc1->signal = signal; in optc1_program_timing()
319 if (optc1->opp_count == 4) in optc1_program_timing()
611 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; in optc1_validate_timing()
1585 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1586 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
1588 optc1->min_h_blank = 32; in dcn10_timing_generator_init()
1589 optc1->min_v_blank = 3; in dcn10_timing_generator_init()
[all …]
A Ddcn10_optc.h585 void optc1_read_otg_state(struct optc *optc1,
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_optc.c32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
207 optc1->opp_count = 1; in optc3_set_odm_bypass()
265 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
354 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
355 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
357 optc1->min_h_blank = 32; in dcn30_timing_generator_init()
358 optc1->min_v_blank = 3; in dcn30_timing_generator_init()
360 optc1->min_h_sync_width = 4; in dcn30_timing_generator_init()
[all …]
A Ddcn30_optc.h313 void dcn30_timing_generator_init(struct optc *optc1);
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_optc.c34 optc1->tg_regs->reg
37 optc1->base.ctx
41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
91 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
278 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
279 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
281 optc1->min_h_blank = 32; in dcn31_timing_generator_init()
282 optc1->min_v_blank = 3; in dcn31_timing_generator_init()
283 optc1->min_v_blank_interlace = 5; in dcn31_timing_generator_init()
284 optc1->min_h_sync_width = 4; in dcn31_timing_generator_init()
[all …]
A Ddcn31_optc.h257 void dcn31_timing_generator_init(struct optc *optc1);

Completed in 717 milliseconds