| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dccg.c | 109 uint32_t otg_inst) in dccg2_otg_add_pixel() argument
113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
114 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_add_pixel()
115 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_add_pixel()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
117 OTG_ADD_PIXEL[otg_inst], 1); in dccg2_otg_add_pixel()
121 uint32_t otg_inst) in dccg2_otg_drop_pixel() argument
126 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_drop_pixel()
127 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_drop_pixel()
128 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
[all …]
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| A D | dcn20_dccg.h | 258 uint32_t otg_inst);
260 uint32_t otg_inst);
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| A D | dcn20_hubp.h | 341 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
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| A D | dcn20_hubp.c | 1052 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) in hubp2_vtg_sel() argument
1056 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); in hubp2_vtg_sel()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_hwseq.c | 140 static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_i… in dmub_abm_set_pipe() argument
149 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; in dmub_abm_set_pipe()
165 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable() local
176 dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE, in dcn21_set_abm_immediate_disable()
185 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_pipe() local
195 dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst); in dcn21_set_pipe()
205 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_backlight_level() local
214 dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl->inst); in dcn21_set_backlight_level()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dccg.h | 78 uint32_t otg_inst);
80 uint32_t otg_inst);
86 int otg_inst);
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| A D | abm.h | 57 bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
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| A D | dwb.h | 175 int otg_inst; member
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| A D | hubp.h | 156 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
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| A D | stream_encoder.h | 252 uint32_t otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dccg.c | 97 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk() argument
102 switch (otg_inst) { in dccg31_enable_dpstreamclk()
128 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_disable_dpstreamclk() argument
136 switch (otg_inst) { in dccg31_disable_dpstreamclk()
162 int otg_inst) in dccg31_set_dpstreamclk() argument
165 dccg31_disable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
167 dccg31_enable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
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| A D | dcn31_dccg.h | 161 int otg_inst);
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| A D | dcn31_hpo_dp_stream_encoder.c | 683 DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, &s->otg_inst); in dcn31_hpo_dp_stream_enc_read_state()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_cp_psp.h | 32 uint8_t otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 530 uint32_t otg_inst: 3; member
1479 uint8_t otg_inst; member
1789 uint8_t otg_inst; member
2001 uint8_t otg_inst; member
2273 uint8_t otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dmub_psr.c | 312 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
314 copy_settings_data->otg_inst = 0; in dmub_psr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_irq.c | 719 if (acrtc->otg_inst == -1) in dm_irq_state()
722 irq_source = dal_irq_type + acrtc->otg_inst; in dm_irq_state()
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| A D | amdgpu_dm_hdcp.c | 473 display->controller = CONTROLLER_ID_D0 + config->otg_inst; in update_config()
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| A D | amdgpu_dm.c | 314 int otg_inst) in get_crtc_by_otg_inst() argument
320 if (WARN_ON(otg_inst == -1)) in get_crtc_by_otg_inst()
326 if (amdgpu_crtc->otg_inst == otg_inst) in get_crtc_by_otg_inst()
2256 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; in dm_gpureset_toggle_interrupts()
6474 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; in dm_set_vupdate_irq()
6507 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; in dm_set_vblank()
7863 acrtc->otg_inst = -1; in amdgpu_dm_crtc_init()
8663 acrtc->otg_inst = -1; in remove_stream()
9582 acrtc->otg_inst = status->primary_otg_inst; in amdgpu_dm_atomic_commit_tail()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 358 unsigned char otg_inst; member
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| A D | display_mode_lib.c | 216 dml_print("DML PARAMS: otg_inst = %d\n", pipe_dest->otg_inst); in dml_log_pipe_params()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_mode.h | 433 int otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hubp.c | 1276 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) in hubp1_vtg_sel() argument
1280 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); in hubp1_vtg_sel()
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| A D | dcn10_hubp.h | 765 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_stream.c | 477 dwb->otg_inst = stream_status->primary_otg_inst; in dc_stream_add_writeback()
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