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Searched refs:pipe_dlg_param (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calcs.c445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1231 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1233 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
1234 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
1250 pipe->pipe_dlg_param.vblank_start = asic_blank_start; in dcn_validate_bandwidth()
1251 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1276 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; in dcn_validate_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hwseq.c698 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
699 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
700 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn20_enable_stream_timing()
701 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_enable_stream_timing()
1304 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1305 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start in dcn20_detect_pipe_changes()
1306 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset in dcn20_detect_pipe_changes()
1307 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) in dcn20_detect_pipe_changes()
1428 &pipe_ctx->pipe_dlg_param); in dcn20_update_dchubp_dpp()
1587 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_program_pipe()
[all …]
A Ddcn20_resource.c3152 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn20_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer.c906 pipe_ctx->pipe_dlg_param.vready_offset, in dcn10_enable_stream_timing()
907 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_enable_stream_timing()
908 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_enable_stream_timing()
909 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn10_enable_stream_timing()
2685 &pipe_ctx->pipe_dlg_param); in dcn10_update_dchubp_dpp()
2841 pipe_ctx->pipe_dlg_param.vready_offset, in dcn10_program_pipe()
2842 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_program_pipe()
2843 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_program_pipe()
2844 pipe_ctx->pipe_dlg_param.vupdate_width); in dcn10_program_pipe()
3574 pipe_ctx->pipe_dlg_param.vstartup_start + 1; in dcn10_get_vupdate_offset_from_vsync()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h380 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member

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