Searched refs:pll_settings (Results 1 – 10 of 10) sorted by relevance
195 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance() argument251 struct pll_settings *pll_settings, in calc_pll_dividers_in_range() argument293 struct pll_settings *pll_settings) in calculate_pixel_clock_pll_dividers() argument397 struct pll_settings *pll_settings) in pll_adjust_pix_clk() argument475 struct pll_settings *pll_settings, in dce110_get_pix_clk_dividers_helper() argument537 struct pll_settings *pll_settings, in dce112_get_pix_clk_dividers_helper() argument567 struct pll_settings *pll_settings) in dce110_get_pix_clk_dividers() argument600 struct pll_settings *pll_settings) in dce112_get_pix_clk_dividers() argument843 struct pll_settings *pll_settings) in dce110_program_pix_clk() argument916 struct pll_settings *pll_settings) in dce112_program_pix_clk() argument[all …]
106 struct pll_settings { struct164 struct pixel_clk_params *, struct pll_settings *);168 struct pll_settings *);
367 struct pll_settings pll_settings; member
1405 pipe_ctx->pll_settings.feedback_divider;1415 pipe_ctx->pll_settings.ss_percentage;1487 &pipe_ctx->pll_settings)) {
923 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
115 &pipes[i].pll_settings); in dp_enable_link_phy()
1108 &pipe_ctx->pll_settings); in build_pipe_hw_param()
898 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()
687 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()
1662 &pipe_ctx->pll_settings); in build_pipe_hw_param()
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