| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_pp_smu.h | 48 struct pp_smu { struct
97 struct pp_smu pp_smu; member
103 void (*set_display_count)(struct pp_smu *pp, int count);
112 void (*set_wm_ranges)(struct pp_smu *pp,
137 void (*set_pme_wa_enable)(struct pp_smu *pp);
168 struct pp_smu pp_smu; member
217 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
269 struct pp_smu pp_smu; member
279 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
287 struct pp_smu pp_smu; member
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| A D | rv1_clk_mgr.c | 210 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
224 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
269 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
287 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
288 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
289 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
300 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_enable_pme_wa()
303 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); in rv1_enable_pme_wa()
[all …]
|
| A D | rv2_clk_mgr.c | 37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
|
| A D | rv2_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
|
| A D | rv1_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 243 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
255 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
256 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
265 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
272 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
293 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) in dcn2_update_clocks()
318 if (pp_smu && pp_smu->set_voltage_by_freq) in dcn2_update_clocks()
418 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_enable_pme_wa()
421 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); in dcn2_enable_pme_wa()
504 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_notify_link_rate_change()
[all …]
|
| A D | dcn20_clk_mgr.h | 43 struct pp_smu_funcs *pp_smu,
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| A D | clk_mgr.c | 224 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
229 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
233 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
238 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
251 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
255 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
259 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
263 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
266 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
277 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_pp_smu.c | 492 static void pp_rv_set_wm_ranges(struct pp_smu *pp, in pp_rv_set_wm_ranges()
544 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp) in pp_rv_set_pme_wa_enable()
639 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk()
657 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq()
681 pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_uclk_by_freq()
705 struct pp_smu *pp, bool pstate_handshake_supported) in pp_nv_set_pstate_handshake_support()
758 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks) in pp_nv_get_maximum_sustainable_clocks()
794 struct pp_smu *pp, struct dpm_clocks *clock_table) in pp_rn_get_dpm_clock_table()
832 funcs->rv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
846 funcs->nv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 528 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
534 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
535 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
938 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
953 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
1014 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
1015 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
|
| A D | rn_clk_mgr.h | 38 struct pp_smu_funcs *pp_smu,
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 1029 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
1653 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn21_pp_smu_create() local
1655 if (!pp_smu) in dcn21_pp_smu_create()
1656 return pp_smu; in dcn21_pp_smu_create()
1658 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1660 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1661 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1664 return pp_smu; in dcn21_pp_smu_create()
1669 if (pp_smu && *pp_smu) { in dcn21_pp_smu_destroy()
1670 kfree(*pp_smu); in dcn21_pp_smu_destroy()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 3450 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); in dcn20_pp_smu_create() local
3452 if (!pp_smu) in dcn20_pp_smu_create()
3453 return pp_smu; in dcn20_pp_smu_create()
3458 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
3460 return pp_smu; in dcn20_pp_smu_create()
3465 if (pp_smu && *pp_smu) { in dcn20_pp_smu_destroy()
3466 kfree(*pp_smu); in dcn20_pp_smu_destroy()
3467 *pp_smu = NULL; in dcn20_pp_smu_destroy()
3683 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
3690 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); in init_soc_bounding_box()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_resource.c | 956 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn10_pp_smu_create() local
958 if (!pp_smu) in dcn10_pp_smu_create()
959 return pp_smu; in dcn10_pp_smu_create()
961 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
962 return pp_smu; in dcn10_pp_smu_create()
1047 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1540 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1546 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1547 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| A D | dcn201_clk_mgr.h | 31 struct pp_smu_funcs *pp_smu,
|
| A D | dcn201_clk_mgr.c | 216 struct pp_smu_funcs *pp_smu, in dcn201_clk_mgr_construct() argument
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.h | 33 struct pp_smu_funcs *pp_smu,
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
|
| A D | dcn31_clk_mgr.c | 632 struct pp_smu_funcs *pp_smu, in dcn31_clk_mgr_construct() argument
640 clk_mgr->base.pp_smu = pp_smu; in dcn31_clk_mgr_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
|
| A D | vg_clk_mgr.c | 732 struct pp_smu_funcs *pp_smu, in vg_clk_mgr_construct() argument
740 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 1351 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1391 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1548 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1549 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr.h | 287 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg …
|
| A D | clk_mgr_internal.h | 230 struct pp_smu_funcs *pp_smu; member
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 221 struct pp_smu_funcs *pp_smu; member
|