| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega20_processpptables.c | 453 pptable->dBtcGbGfxCksOn.a,
454 pptable->dBtcGbGfxCksOn.b,
455 pptable->dBtcGbGfxCksOn.c);
461 pptable->dBtcGbGfxAfll.a,
462 pptable->dBtcGbGfxAfll.b,
463 pptable->dBtcGbGfxAfll.c);
465 pptable->dBtcGbSoc.a,
466 pptable->dBtcGbSoc.b,
467 pptable->dBtcGbSoc.c);
961 kfree(hwmgr->pptable); in vega20_pp_tables_uninitialize()
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| A D | process_pptables_v1_0.c | 205 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_platform_power_management_table()
484 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_pcie_table()
762 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_gpio_table()
794 (struct phm_ppt_v1_information *)(hwmgr->pptable); in init_clock_voltage_dependency()
1148 PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), in pp_tables_v1_0_initialize()
1193 (struct phm_ppt_v1_information *)(hwmgr->pptable); in pp_tables_v1_0_uninitialize()
1231 kfree(hwmgr->pptable); in pp_tables_v1_0_uninitialize()
1232 hwmgr->pptable = NULL; in pp_tables_v1_0_uninitialize()
1315 + le16_to_cpu(pptable->usVCEStateTableOffset)); in ppt_get_vce_state_table_entry_v1_0()
1317 + le16_to_cpu(pptable->usSclkDependencyTableOffset)); in ppt_get_vce_state_table_entry_v1_0()
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| A D | vega12_processpptables.c | 196 (struct phm_ppt_v3_information *)hwmgr->pptable; in init_powerplay_table_information()
270 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); in vega12_pp_tables_initialize()
271 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega12_pp_tables_initialize()
297 (struct phm_ppt_v3_information *)(hwmgr->pptable); in vega12_pp_tables_uninitialize()
314 kfree(hwmgr->pptable); in vega12_pp_tables_uninitialize()
315 hwmgr->pptable = NULL; in vega12_pp_tables_uninitialize()
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| A D | vega10_hwmgr.c | 198 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_set_features_platform_caps()
308 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_odn_initial_default_setting()
523 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_socclk_for_voltage_evv()
560 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_evv_voltages()
665 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_patch_voltage_dependency_tables_with_lookup_table()
741 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_complete_dependency_tables()
770 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_set_private_data_based_on_pptable()
1164 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_construct_voltage_tables()
1920 (hwmgr->pptable); in vega10_populate_single_display_type()
4700 gen_speed = pptable->PcieGenSpeed[i]; in vega10_print_clock_levels()
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| A D | vega10_processpptables.c | 790 (struct phm_ppt_v2_information *)(hwmgr->pptable); in get_pcie_table()
878 (struct phm_ppt_v2_information *)(hwmgr->pptable); in init_powerplay_extended_tables()
1066 (struct phm_ppt_v2_information *)(hwmgr->pptable); in init_dpm_2_parameters()
1153 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL); in vega10_pp_tables_initialize()
1155 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega10_pp_tables_initialize()
1200 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_pp_tables_uninitialize()
1238 kfree(hwmgr->pptable); in vega10_pp_tables_uninitialize()
1239 hwmgr->pptable = NULL; in vega10_pp_tables_uninitialize()
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| A D | smu7_hwmgr.c | 321 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_construct_voltage_tables()
640 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_default_pcie_table()
872 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_dpm_tables_v1()
938 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_odn_initial_default_setting()
983 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_voltage_range_from_vbios()
1011 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_check_dpm_table_updated()
2004 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_evv_voltages()
5115 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_sclks()
5152 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_mclks()
5197 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_sclks_with_latency()
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| A D | smu_helper.c | 467 (struct phm_ppt_v1_information *)(hwmgr->pptable); in phm_get_sclk_for_voltage_evv()
496 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in phm_initializa_dynamic_state_adjustment_rule_settings()
548 (struct phm_ppt_v1_information *)hwmgr->pptable; in phm_apply_dal_min_voltage_request()
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| A D | vega12_thermal.c | 174 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_thermal_set_temperature_range()
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| A D | vega20_thermal.c | 245 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_thermal_set_temperature_range()
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| A D | vega20_hwmgr.c | 788 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_init_smc_table()
1041 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_od8_set_feature_capabilities()
1241 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_od8_initialize_default_settings()
2792 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega20_get_dal_power_level()
3361 PPTable_t *pptable = &(data->smc_state_table.pp_table); in vega20_print_clock_levels() local
3460 gen_speed = pptable->PcieGenSpeed[i]; in vega20_print_clock_levels()
3461 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3474 pptable->LclkFreq[i], in vega20_print_clock_levels()
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| A D | vega10_thermal.c | 364 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_thermal_set_temperature_range()
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| A D | vega10_powertune.c | 1267 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_initialize_power_tune_defaults()
1318 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_enable_power_containment()
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| A D | smu10_hwmgr.c | 457 struct smu10_voltage_dependency_table **pptable, in smu10_get_clock_voltage_dependency_table() argument
475 *pptable = ptable; in smu10_get_clock_voltage_dependency_table()
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| A D | smu7_powertune.c | 1154 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_enable_power_containment()
1244 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_power_control_set_level()
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| A D | vega12_hwmgr.c | 819 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_init_smc_table()
1799 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega12_get_dal_power_level()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | sienna_cichlid_ppt.c | 2590 pptable->dBtcGbGfxPll.a, in beige_goby_dump_pptable()
2591 pptable->dBtcGbGfxPll.b, in beige_goby_dump_pptable()
2592 pptable->dBtcGbGfxPll.c); in beige_goby_dump_pptable()
2598 pptable->dBtcGbSoc.a, in beige_goby_dump_pptable()
2599 pptable->dBtcGbSoc.b, in beige_goby_dump_pptable()
2600 pptable->dBtcGbSoc.c); in beige_goby_dump_pptable()
3228 pptable->dBtcGbGfxPll.a, in sienna_cichlid_dump_pptable()
3229 pptable->dBtcGbGfxPll.b, in sienna_cichlid_dump_pptable()
3236 pptable->dBtcGbSoc.a, in sienna_cichlid_dump_pptable()
3237 pptable->dBtcGbSoc.b, in sienna_cichlid_dump_pptable()
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| A D | arcturus_ppt.c | 1359 if (!pptable) { in arcturus_get_power_limit()
1875 pptable->dBtcGbGfxPll.a, in arcturus_dump_pptable()
1876 pptable->dBtcGbGfxPll.b, in arcturus_dump_pptable()
1877 pptable->dBtcGbGfxPll.c); in arcturus_dump_pptable()
1879 pptable->dBtcGbGfxAfll.a, in arcturus_dump_pptable()
1880 pptable->dBtcGbGfxAfll.b, in arcturus_dump_pptable()
1881 pptable->dBtcGbGfxAfll.c); in arcturus_dump_pptable()
1883 pptable->dBtcGbSoc.a, in arcturus_dump_pptable()
1884 pptable->dBtcGbSoc.b, in arcturus_dump_pptable()
1885 pptable->dBtcGbSoc.c); in arcturus_dump_pptable()
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| A D | navi10_ppt.c | 1243 dpm_desc = &pptable->DpmDescriptor[clk_index]; in navi10_is_support_fine_grained_dpm()
1350 pptable->LclkFreq[i], in navi10_print_clk_levels()
1706 smu->fan_max_rpm = pptable->FanMaximumRpm; in navi10_get_fan_parameters()
2002 *(uint32_t *)data = pptable->FanMaximumRpm; in navi10_read_sensor()
2106 range->max = pptable->TedgeLimit * in navi10_get_thermal_temperature_range()
2114 range->mem_crit_max = pptable->TmemLimit * in navi10_get_thermal_temperature_range()
2160 if (!pptable) { in navi10_get_power_limit()
2207 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : in navi10_update_pcie_parameters()
2209 pptable->PcieLaneCount[i] : pcie_width_cap); in navi10_update_pcie_parameters()
2218 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) in navi10_update_pcie_parameters()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | vegam_smumgr.c | 336 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_uvd_smc_table()
369 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_vce_smc_table()
401 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_bif_smc_table()
436 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_initialize_power_tune_defaults()
508 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_cac_table()
545 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_ulv_level()
818 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_single_graphic_level()
871 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_all_graphic_levels()
987 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_single_memory_level()
1091 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_mvdd_value()
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| A D | polaris10_smumgr.c | 434 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_parameters_in_dpm_table()
508 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_tdc_limit()
588 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_vddc_base_leakage_sidd()
748 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_cac_table()
783 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_ulv_level()
963 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_single_graphic_level()
1042 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_all_graphic_levels()
1158 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_single_memory_level()
1257 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_mvdd_value()
1284 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_smc_acpi_level()
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| A D | fiji_smumgr.c | 471 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_initialize_power_tune_defaults()
493 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_parameters_in_dpm_table()
587 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_tdc_limit()
673 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_vddc_base_leakage_sidd()
761 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_cac_table()
801 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_ulv_level()
944 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_single_graphic_level()
1006 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_all_graphic_levels()
1166 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_single_memory_level()
1276 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_mvdd_value()
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| A D | tonga_smumgr.c | 253 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_get_dependency_volt_by_clk()
398 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_cac_tables()
483 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_ulv_level()
1148 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_mvdd_value()
1583 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_clock_stretcher_data_table()
1833 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_bapm_parameters_in_dpm_table()
1894 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_tdc_limit()
1978 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_bapm_vddc_base_leakage_sidd()
2228 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_init_smc_table()
2681 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_update_uvd_smc_table()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | aldebaran_ppt.c | 295 PPTable_t *pptable = smu->smu_table.driver_pptable; in aldebaran_set_default_dpm_table() local
319 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin; in aldebaran_set_default_dpm_table()
321 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; in aldebaran_set_default_dpm_table()
1043 PPTable_t *pptable = smu->smu_table.driver_pptable; in aldebaran_get_thermal_temperature_range() local
1050 range->hotspot_crit_max = pptable->ThotspotLimit * in aldebaran_get_thermal_temperature_range()
1054 range->mem_crit_max = pptable->TmemLimit * in aldebaran_get_thermal_temperature_range()
1195 PPTable_t *pptable = smu->smu_table.driver_pptable; in aldebaran_get_power_limit() local
1222 if (!pptable) { in aldebaran_get_power_limit()
1227 power_limit = pptable->PptLimit; in aldebaran_get_power_limit()
1237 if (pptable) in aldebaran_get_power_limit()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/ |
| A D | smu_cmn.c | 936 void *pptable = smu->smu_table.driver_pptable; in smu_cmn_write_pptable() local
941 pptable, in smu_cmn_write_pptable()
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| /linux/drivers/gpu/drm/amd/pm/inc/ |
| A D | hwmgr.h | 772 void *pptable; member
|