Home
last modified time | relevance | path

Searched refs:rFPGA0_XB_LSSIParameter (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/staging/rtl8192u/
A Dr819xU_phyreg.h19 #define rFPGA0_XB_LSSIParameter 0x844 macro
A Dr819xU_phy.c589 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl8192_InitBBRFRegDef()
/linux/drivers/staging/rtl8192e/rtl8192e/
A Dr8192E_phyreg.h62 #define rFPGA0_XB_LSSIParameter 0x844 macro
A Dr8192E_phy.c403 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
/linux/drivers/staging/rtl8712/
A Drtl871x_mp_phy_regdef.h102 #define rFPGA0_XB_LSSIParameter 0x844 macro
/linux/drivers/staging/r8188eu/hal/
A DHalPhyRf_8188e.c848 ODM_SetBBReg(dm_odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); in phy_IQCalibrate_8188E()
925 ODM_SetBBReg(dm_odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); in phy_IQCalibrate_8188E()
A Drtl8188e_phycfg.c414 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in phy_InitBBRFRegisterDefinition()
/linux/drivers/staging/rtl8723bs/include/
A DHal8192CPhyReg.h114 #define rFPGA0_XB_LSSIParameter 0x844 macro
/linux/drivers/staging/r8188eu/include/
A DHal8188EPhyReg.h70 #define rFPGA0_XB_LSSIParameter 0x844 macro
/linux/drivers/staging/rtl8723bs/hal/
A Drtl8723b_phycfg.c323 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in phy_InitBBRFRegisterDefinition()

Completed in 37 milliseconds