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Searched refs:reg1 (Results 1 – 25 of 153) sorted by relevance

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/linux/arch/nios2/include/asm/
A Dasm-macros.h22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
62 xori \reg1, \reg1, %lo(\mask)
98 BT \reg1, \reg2, \bit
99 beq \reg1, r0, \label
110 BT \reg1, \reg2, \bit
111 bne \reg1, r0, \label
187 beq \reg1, r0, \label
200 bne \reg1, r0, \label
[all …]
/linux/arch/arm64/include/asm/
A Dkvm_ptrauth.h27 mrs_s \reg1, SYS_APIAKEYLO_EL1
30 mrs_s \reg1, SYS_APIBKEYLO_EL1
33 mrs_s \reg1, SYS_APDAKEYLO_EL1
36 mrs_s \reg1, SYS_APDBKEYLO_EL1
39 mrs_s \reg1, SYS_APGAKEYLO_EL1
73 mrs \reg1, hcr_el2
74 and \reg1, \reg1, #(HCR_API | HCR_APK)
75 cbz \reg1, .L__skip_switch\@
85 mrs \reg1, hcr_el2
86 and \reg1, \reg1, #(HCR_API | HCR_APK)
[all …]
A Dkvm_mte.h18 mrs \reg1, hcr_el2
21 mrs_s \reg1, SYS_RGSR_EL1
23 mrs_s \reg1, SYS_GCR_EL1
24 str \reg1, [\h_ctxt, #CPU_GCR_EL1]
27 msr_s SYS_RGSR_EL1, \reg1
29 msr_s SYS_GCR_EL1, \reg1
38 mrs \reg1, hcr_el2
41 mrs_s \reg1, SYS_RGSR_EL1
43 mrs_s \reg1, SYS_GCR_EL1
47 msr_s SYS_RGSR_EL1, \reg1
[all …]
/linux/arch/s390/include/asm/
A Dap.h67 : [reg1] "+&d" (reg1) in ap_instructions_available()
91 : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2) in ap_tapq()
96 return reg1; in ap_tapq()
131 : [reg1] "=&d" (reg1) in ap_rapq()
152 : [reg1] "=&d" (reg1) in ap_zapq()
196 : [reg1] "+&d" (reg1) in ap_qci()
240 } reg1; in ap_aqic() local
251 : [reg1] "+&d" (reg1) in ap_aqic()
291 } reg1; in ap_qact() local
302 : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2) in ap_qact()
[all …]
/linux/arch/arm/probes/kprobes/
A Dtest-core.h241 TEST_ARG_REG(reg1, val1) \
249 TEST_ARG_REG(reg1, val1) \
258 TEST_ARG_REG(reg1, val1) \
268 TEST_ARG_PTR(reg1, val1) \
275 TEST_ARG_PTR(reg1, val1) \
283 TEST_ARG_REG(reg1, val1) \
291 TEST_ARG_PTR(reg1, val1) \
300 TEST_ARG_REG(reg1, val1) \
309 TEST_ARG_REG(reg1, val1) \
318 TEST_ARG_PTR(reg1, val1) \
[all …]
/linux/arch/x86/events/intel/
A Duncore_nhmex.c371 reg1->idx = 0; in nhmex_bbox_hw_config()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
456 reg1->idx = 0; in nhmex_sbox_hw_config()
470 wrmsrl(reg1->reg + 1, reg1->config); in nhmex_sbox_msr_enable_event()
750 reg1->alloc = 0; in nhmex_mbox_put_constraint()
951 reg1->idx--; in nhmex_rbox_alter_er()
954 reg1->idx++; in nhmex_rbox_alter_er()
1055 reg1->alloc = 1; in nhmex_rbox_get_constraint()
1083 reg1->alloc = 0; in nhmex_rbox_put_constraint()
1098 reg1->idx = idx; in nhmex_rbox_hw_config()
[all …]
A Duncore_snbep.c940 reg1->alloc = 0; in snbep_cbox_put_constraint()
1126 reg1->alloc = 0; in snbep_pcu_put_constraint()
1138 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); in snbep_pcu_hw_config()
1191 reg1->idx = 0; in snbep_qpi_hw_config()
2593 reg1->idx = 0; in hswep_ubox_hw_config()
2847 reg1->config = event->attr.config1 & (0xff << reg1->idx); in hswep_pcu_hw_config()
4384 reg1->idx = 0; in snr_cha_hw_config()
4396 wrmsrl(reg1->reg, reg1->config); in snr_cha_enable_event()
4596 reg1->config = event->attr.config1 & (0xff << reg1->idx); in snr_pcu_hw_config()
5052 reg1->idx = 0; in icx_cha_hw_config()
[all …]
/linux/arch/arm/kernel/
A Dhyp-stub.S29 .macro store_primary_cpu_mode reg1, reg2
30 mrs \reg1, cpsr
31 and \reg1, \reg1, #MODE_MASK
32 str_l \reg1, __boot_cpu_mode, \reg2
41 .macro compare_cpu_mode_with_primary mode, reg1, reg2
43 ldr \reg1, [\reg2]
44 cmp \mode, \reg1 @ matches primary CPU boot mode?
45 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
46 strne \reg1, [\reg2] @ record what happened and give up
51 .macro store_primary_cpu_mode reg1:req, reg2:req
[all …]
/linux/arch/arm/lib/
A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
94 .macro enter reg1 reg2
96 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
99 .macro usave reg1 reg2
100 UNWIND( .save {r0, r2, r3, \reg1, \reg2} )
103 .macro exit reg1 reg2
[all …]
A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 .macro enter reg1 reg2
46 stmdb sp!, {r0, \reg1, \reg2}
49 .macro usave reg1 reg2
50 UNWIND( .save {r0, \reg1, \reg2} )
53 .macro exit reg1 reg2
[all …]
A Dcsumpartialcopy.S25 .macro load1b, reg1
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
93 .macro enter reg1 reg2
95 stmdb sp!, {r0, r2, r3, \reg1, \reg2}
98 .macro usave reg1 reg2
99 UNWIND( .save {r0, r2, r3, \reg1, \reg2} )
102 .macro exit reg1 reg2
[all …]
A Dcsumpartialcopyuser.S38 .macro load1b, reg1
39 ldrusr \reg1, r0, 1
42 .macro load2b, reg1, reg2
43 ldrusr \reg1, r0, 1
47 .macro load1l, reg1
48 ldrusr \reg1, r0, 4
51 .macro load2l, reg1, reg2
52 ldrusr \reg1, r0, 4
56 .macro load4l, reg1, reg2, reg3, reg4
57 ldrusr \reg1, r0, 4
/linux/sound/pci/ice1712/
A Dwm8776.c137 .reg1 = WM8776_REG_DACLVOL,
163 .reg1 = WM8776_REG_HPLVOL,
181 .reg1 = WM8776_REG_HPLVOL,
190 .reg1 = WM8776_REG_OUTMUX,
196 .reg1 = WM8776_REG_OUTMUX,
234 .reg1 = WM8776_REG_ADCMUX,
243 .reg1 = WM8776_REG_ADCMUX,
249 .reg1 = WM8776_REG_ADCMUX,
255 .reg1 = WM8776_REG_ADCMUX,
261 .reg1 = WM8776_REG_ADCMUX,
[all …]
A Dwm8766.c34 .reg1 = WM8766_REG_DACL1,
45 .reg1 = WM8766_REG_DACL2,
56 .reg1 = WM8766_REG_DACL3,
66 .reg1 = WM8766_REG_DACCTRL2,
73 .reg1 = WM8766_REG_DACCTRL2,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_IFCTRL,
93 .reg1 = WM8766_REG_IFCTRL,
99 .reg1 = WM8766_REG_IFCTRL,
105 .reg1 = WM8766_REG_DACCTRL2,
[all …]
/linux/arch/arm64/crypto/
A Daes-cipher-core.S20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
23 ubfiz \reg1, \in1e, #2, #8
26 ubfx \reg1, \in1e, #\shift, #8
38 ldr \reg1, [tt, \reg1, uxtw #2]
42 lsl \reg1, \reg1, #2
45 ldrb \reg1, [tt, \reg1, uxtw]
49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
51 ubfx \reg1, \in1d, #\shift, #8
53 ldr\op \reg1, [tt, \reg1, uxtw #\sz]
/linux/drivers/rtc/
A Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
38 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
40 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
41 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
62 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/linux/drivers/media/dvb-frontends/
A Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/linux/arch/s390/kvm/
A Dpriv.c249 int reg1, reg2; in handle_iske() local
288 vcpu->run->s.regs.gprs[reg1] &= ~0xff; in handle_iske()
289 vcpu->run->s.regs.gprs[reg1] |= key; in handle_iske()
296 int reg1, reg2; in handle_rrbe() local
347 int reg1, reg2; in handle_sske() local
989 int reg1, reg2; in handle_epsw() local
1019 int reg1, reg2; in handle_pfmf() local
1309 reg = reg1; in kvm_s390_handle_lctl()
1344 reg = reg1; in kvm_s390_handle_stctl()
1382 reg = reg1; in handle_lctlg()
[all …]
A Dtrace.h287 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
288 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
293 __field(int, reg1)
301 __entry->reg1 = reg1;
308 __entry->reg1, __entry->reg3, __entry->addr)
312 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
313 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
318 __field(int, reg1)
326 __entry->reg1 = reg1;
333 __entry->reg1, __entry->reg3, __entry->addr)
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/linux/arch/s390/boot/
A Dmem_detect.c69 unsigned long reg1, reg2, ry; in __diag260() local
89 : [reg1] "=&d" (reg1), in __diag260()
123 unsigned long reg1, reg2; in tprot() local
138 : [reg1] "=&d" (reg1), in tprot()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 .enable_reg = SRI(reg1, block, reg_num),\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
227 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
228 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
236 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
237 .enable_reg = SRI_DMUB(reg1),\
239 reg1 ## __ ## mask1 ## _MASK,\
241 reg1 ## __ ## mask1 ## _MASK,\
242 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
214 .enable_reg = SRI_DMUB(reg1),\
216 reg1 ## __ ## mask1 ## _MASK,\
218 reg1 ## __ ## mask1 ## _MASK,\
219 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
224 .enable_reg = SRI_DMUB(reg1),\
226 reg1 ## __ ## mask1 ## _MASK,\
228 reg1 ## __ ## mask1 ## _MASK,\
229 ~reg1 ## __ ## mask1 ## _MASK \

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