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Searched refs:reg_off (Results 1 – 25 of 52) sorted by relevance

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/linux/drivers/mmc/host/
A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
49 #define MIO_EMM_RCA(x) (0xa0 + x->reg_off)
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_vbif.c59 u32 reg_off; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
90 u32 reg_off; in dpu_hw_set_limit_conf() local
94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
111 u32 reg_off; in dpu_hw_get_limit_conf() local
116 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_get_limit_conf()
118 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_get_limit_conf()
[all …]
A Ddpu_hw_catalog.c261 .reg_off = 0x2AC, .bit_off = 0},
263 .reg_off = 0x2B4, .bit_off = 0},
265 .reg_off = 0x2BC, .bit_off = 0},
286 .reg_off = 0x2AC, .bit_off = 0},
288 .reg_off = 0x2AC, .bit_off = 8},
290 .reg_off = 0x2B4, .bit_off = 8},
292 .reg_off = 0x2C4, .bit_off = 8},
329 .reg_off = 0x2AC, .bit_off = 0},
331 .reg_off = 0x2AC, .bit_off = 8},
333 .reg_off = 0x2B4, .bit_off = 8},
[all …]
A Ddpu_hw_top.c95 u32 reg_off, bit_off; in dpu_hw_setup_clk_force_ctrl() local
107 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl()
110 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl()
117 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
A Ddpu_hw_util.c76 u32 reg_off, in dpu_reg_write() argument
83 name, c->blk_off + reg_off, val); in dpu_reg_write()
84 writel_relaxed(val, c->base_off + c->blk_off + reg_off); in dpu_reg_write()
87 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off) in dpu_reg_read() argument
89 return readl_relaxed(c->base_off + c->blk_off + reg_off); in dpu_reg_read()
/linux/drivers/pinctrl/
A Dpinctrl-digicolor.c129 int bit_off, reg_off; in dc_set_mux() local
132 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
134 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
137 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
147 int bit_off, reg_off; in dc_pmx_request_gpio() local
150 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
152 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
176 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
178 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
198 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_output()
[all …]
/linux/drivers/irqchip/
A Dirq-davinci-aintc.c82 unsigned int irq_off, reg_off, prio, shift; in davinci_aintc_init() local
125 for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; in davinci_aintc_init()
126 reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { in davinci_aintc_init()
129 davinci_aintc_writel(prio, reg_off); in davinci_aintc_init()
156 for (irq_off = 0, reg_off = 0; in davinci_aintc_init()
158 irq_off += 32, reg_off += 0x04) in davinci_aintc_init()
159 davinci_aintc_setup_gc(davinci_aintc_base + reg_off, in davinci_aintc_init()
/linux/drivers/clk/meson/
A Daxg.c29 .reg_off = HHI_MPLL_CNTL,
34 .reg_off = HHI_MPLL_CNTL,
39 .reg_off = HHI_MPLL_CNTL,
44 .reg_off = HHI_MPLL_CNTL2,
49 .reg_off = HHI_MPLL_CNTL,
54 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
A Dg12a-aoclk.c122 .reg_off = AO_RTC_ALT_CLK_CNTL0,
127 .reg_off = AO_RTC_ALT_CLK_CNTL0,
132 .reg_off = AO_RTC_ALT_CLK_CNTL1,
137 .reg_off = AO_RTC_ALT_CLK_CNTL1,
142 .reg_off = AO_RTC_ALT_CLK_CNTL0,
213 .reg_off = AO_CEC_CLK_CNTL_REG0,
218 .reg_off = AO_CEC_CLK_CNTL_REG0,
223 .reg_off = AO_CEC_CLK_CNTL_REG1,
228 .reg_off = AO_CEC_CLK_CNTL_REG1,
233 .reg_off = AO_CEC_CLK_CNTL_REG0,
A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
A Dgxbb.c89 .reg_off = HHI_MPLL_CNTL,
94 .reg_off = HHI_MPLL_CNTL,
99 .reg_off = HHI_MPLL_CNTL,
104 .reg_off = HHI_MPLL_CNTL2,
109 .reg_off = HHI_MPLL_CNTL,
114 .reg_off = HHI_MPLL_CNTL,
718 .reg_off = HHI_MPLL_CNTL7,
723 .reg_off = HHI_MPLL_CNTL7,
728 .reg_off = HHI_MPLL_CNTL7,
761 .reg_off = HHI_MPLL_CNTL8,
[all …]
A Dg12a.c33 .reg_off = HHI_FIX_PLL_CNTL0,
38 .reg_off = HHI_FIX_PLL_CNTL0,
43 .reg_off = HHI_FIX_PLL_CNTL0,
48 .reg_off = HHI_FIX_PLL_CNTL1,
53 .reg_off = HHI_FIX_PLL_CNTL0,
58 .reg_off = HHI_FIX_PLL_CNTL0,
102 .reg_off = HHI_SYS_PLL_CNTL0,
107 .reg_off = HHI_SYS_PLL_CNTL0,
112 .reg_off = HHI_SYS_PLL_CNTL0,
117 .reg_off = HHI_SYS_PLL_CNTL0,
[all …]
A Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
A Dgxbb-aoclk.c89 .reg_off = AO_RTC_ALT_CLK_CNTL0,
94 .reg_off = AO_RTC_ALT_CLK_CNTL0,
99 .reg_off = AO_RTC_ALT_CLK_CNTL1,
104 .reg_off = AO_RTC_ALT_CLK_CNTL1,
109 .reg_off = AO_RTC_ALT_CLK_CNTL0,
A Daxg-aoclk.c103 .reg_off = AO_RTC_ALT_CLK_CNTL0,
108 .reg_off = AO_RTC_ALT_CLK_CNTL0,
113 .reg_off = AO_RTC_ALT_CLK_CNTL1,
118 .reg_off = AO_RTC_ALT_CLK_CNTL1,
123 .reg_off = AO_RTC_ALT_CLK_CNTL0,
A Dmeson8b.c58 .reg_off = HHI_MPLL_CNTL,
63 .reg_off = HHI_MPLL_CNTL,
68 .reg_off = HHI_MPLL_CNTL,
73 .reg_off = HHI_MPLL_CNTL2,
78 .reg_off = HHI_MPLL_CNTL,
83 .reg_off = HHI_MPLL_CNTL,
472 .reg_off = HHI_MPLL_CNTL7,
477 .reg_off = HHI_MPLL_CNTL7,
482 .reg_off = HHI_MPLL_CNTL7,
487 .reg_off = HHI_MPLL_CNTL,
[all …]
/linux/drivers/pinctrl/spear/
A Dpinctrl-plgpio.c83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set() local
84 u32 val = readl_relaxed(reg_off); in is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set() local
93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set()
95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set()
102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset()
104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset()
323 void __iomem *reg_off; in plgpio_irq_set_type() local
341 val = readl_relaxed(reg_off); in plgpio_irq_set_type()
345 writel_relaxed(val | (1 << offset), reg_off); in plgpio_irq_set_type()
[all …]
/linux/drivers/thermal/samsung/
A Dexynos_tmu.c452 unsigned int reg_off, j; in exynos5433_tmu_set_trip_temp() local
456 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; in exynos5433_tmu_set_trip_temp()
463 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_temp()
466 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_temp()
472 unsigned int reg_off, j; in exynos5433_tmu_set_trip_hyst() local
483 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
486 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
525 unsigned int reg_off, bit_off; in exynos7_tmu_set_trip_temp() local
528 reg_off = ((7 - trip) / 2) * 4; in exynos7_tmu_set_trip_temp()
540 unsigned int reg_off, bit_off; in exynos7_tmu_set_trip_hyst() local
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
A Docteon_device.h740 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
741 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
743 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
744 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
746 #define octeon_read_csr(oct_dev, reg_off) \ argument
747 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
749 #define octeon_read_csr64(oct_dev, reg_off) \ argument
750 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/linux/arch/x86/kvm/
A Dlapic.h156 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
158 return *((u32 *) (apic->regs + reg_off)); in kvm_lapic_get_reg()
161 static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val) in __kvm_lapic_set_reg() argument
163 *((u32 *) (regs + reg_off)) = val; in __kvm_lapic_set_reg()
166 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
168 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
/linux/drivers/misc/habanalabs/goya/
A Dgoya.c1035 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1036 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1044 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off, in goya_init_dma_qman()
1048 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002); in goya_init_dma_qman()
1049 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008); in goya_init_dma_qman()
1076 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off, in goya_init_dma_ch()
1884 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0); in goya_init_tpc_qman()
1885 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0); in goya_init_tpc_qman()
1896 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008); in goya_init_tpc_qman()
1901 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off, in goya_init_tpc_qman()
[all …]
/linux/sound/soc/xilinx/
A Dxlnx_i2s.c42 u32 reg_off, chan_id; in xlnx_i2s_hw_params() local
48 reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4); in xlnx_i2s_hw_params()
49 writel(chan_id, base + reg_off); in xlnx_i2s_hw_params()
/linux/drivers/mtd/nand/raw/
A Dqcom_nandc.c862 int reg_off, const void *vaddr, in prep_bam_dma_desc_cmd() argument
876 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
882 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
1678 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; in qcom_nandc_read_cw_raw() local
1721 reg_off += data_size1; in qcom_nandc_read_cw_raw()
1724 reg_off += oob_size1; in qcom_nandc_read_cw_raw()
1727 reg_off += data_size2; in qcom_nandc_read_cw_raw()
2183 int reg_off = FLASH_BUF_ACC; in qcom_nandc_write_page_raw() local
2200 reg_off += data_size1; in qcom_nandc_write_page_raw()
2205 reg_off += oob_size1; in qcom_nandc_write_page_raw()
[all …]
/linux/drivers/clk/
A Dclk-stm32mp1.c332 u32 reg_off; member
343 u32 reg_off; member
351 u32 reg_off; member
1162 .reg_off = _offset,\
1190 .reg_off = _offset,\
1211 .reg_off = _offset,\
1264 .reg_off = _gate_offset,\
1298 .reg_off = _div_offset,\
1318 .reg_off = _offset,\
1485 .reg_off = _gate_offset,\
[all …]
/linux/drivers/crypto/keembay/
A Docs-hcu.c376 int reg_off; in ocs_hcu_clear_key() local
379 for (reg_off = 0; reg_off < OCS_HCU_HW_KEY_LEN; reg_off += sizeof(u32)) in ocs_hcu_clear_key()
380 writel(0, hcu_dev->io_base + OCS_HCU_KEY_0 + reg_off); in ocs_hcu_clear_key()

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