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Searched refs:res_cap (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.c1082 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1112 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1125 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1130 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1137 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1160 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1207 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1232 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1429 pool->base.res_cap = &res_cap_dcn301; in dcn301_resource_construct()
1646 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c845 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
880 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1151 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1181 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1194 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1206 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1230 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1498 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1656 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_construct()
1701 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c787 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
822 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
1077 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1107 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
1120 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1132 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1156 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1438 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1587 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_construct()
1632 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_resource.c372 static const struct resource_caps res_cap = { variable
821 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
951 pool->base.res_cap = &res_cap; in dce60_construct()
959 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
960 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1072 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1145 pool->base.res_cap = &res_cap_61; in dce61_construct()
1269 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1342 pool->base.res_cap = &res_cap_64; in dce64_construct()
1462 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
/linux/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_resource.c377 static const struct resource_caps res_cap = { variable
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
956 pool->base.res_cap = &res_cap; in dce80_construct()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
965 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1083 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1156 pool->base.res_cap = &res_cap_81; in dce81_construct()
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1355 pool->base.res_cap = &res_cap_83; in dce83_construct()
1477 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c1550 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1580 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1593 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1605 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1628 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1678 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1703 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
2187 pool->base.res_cap = &res_cap_dcn31; in dcn31_resource_construct()
2370 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_construct()
2420 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_construct()
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A Ddcn31_hwseq.c196 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn31_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_enc_cfg.c38 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
170 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
263 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_init()
492 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
606 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
A Ddc.c280 link->dc->res_pool->res_cap->num_hpo_dp_link_encoder > 0) { in create_links()
282 if (i < link->dc->res_pool->res_cap->num_hpo_dp_link_encoder) { in create_links()
323 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
324 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
363 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in destroy_link_encoders()
364 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in destroy_link_encoders()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c1228 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1258 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1271 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1283 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1359 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1384 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1667 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
2579 pool->base.res_cap = &res_cap_dcn3; in dcn30_resource_construct()
2773 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_construct()
2822 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_construct()
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A Ddcn30_hwseq.c388 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
418 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
532 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn30_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/dce100/
A Ddce100_resource.c376 static const struct resource_caps res_cap = { variable
778 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
990 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1065 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1066 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1121 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_resource.c498 static const struct resource_caps res_cap = { variable
625 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1066 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1216 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_resource.c954 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
959 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1088 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1186 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1221 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1230 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1246 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
A Ddcn201_hwseq.c183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
307 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
340 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c930 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
960 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
973 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
978 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
985 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1598 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in update_bw_bounding_box()
1963 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1967 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct()
1978 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
2194 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_resource.c549 static const struct resource_caps res_cap = { variable
1011 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1394 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1396 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1410 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1619 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
A Ddcn10_hw_sequencer.c403 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn10_log_hw_state()
1299 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn10_init_pipes()
1461 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn10_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c1474 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1504 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1517 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1529 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1701 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1715 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1729 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
3401 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
3424 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
3737 pool->base.res_cap = &res_cap_nv14; in dcn20_resource_construct()
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A Ddcn20_hwseq.c301 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
310 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
2533 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn20_fpga_init_hw()
2568 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/dce112/
A Ddce112_resource.c799 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1227 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1234 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1235 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1368 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_resource.c837 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1358 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1365 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1367 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1482 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h295 const struct resource_caps *res_cap; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c260 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn301_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_i2c_hw.c407 if (line < pool->res_cap->num_ddc) in acquire_i2c_hw_engine()

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