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Searched refs:sdhci_readl (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/mmc/host/
A Dsdhci-of-esdhc.c842 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_reset()
892 val = sdhci_readl(host, ESDHC_PROCTL); in esdhc_signal_voltage_switch()
953 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_block_enable()
969 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_window_ptr()
977 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_window_ptr()
983 val = sdhci_readl(host, ESDHC_TBSTAT); in esdhc_tuning_window_ptr()
984 val = sdhci_readl(host, ESDHC_TBSTAT); in esdhc_tuning_window_ptr()
1041 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_execute_sw_tuning()
1091 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_execute_tuning()
1174 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_set_uhs_signaling()
[all …]
A Dsdhci-xenon-phy.c235 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
265 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
331 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
336 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
420 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
454 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
556 reg = sdhci_readl(host, phy_regs->pad_ctrl); in xenon_emmc_phy_set()
600 reg = sdhci_readl(host, phy_regs->pad_ctrl2); in xenon_emmc_phy_set()
609 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_emmc_phy_set()
613 reg = sdhci_readl(host, phy_regs->func_ctrl); in xenon_emmc_phy_set()
[all …]
A Dsdhci-xenon.c30 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
58 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
74 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg()
88 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
106 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
117 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
127 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
144 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
147 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup()
399 reg = sdhci_readl(host, XENON_SYS_CFG_INFO); in xenon_enable_sdio_irq()
[all …]
A Dsdhci-bcm-kona.c67 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
71 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset()
79 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
99 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
104 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
138 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
A Dsdhci_f_sdh30.c35 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
47 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
52 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
73 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
162 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
167 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
A Dsdhci-pci-gli.c145 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on()
162 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off()
187 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
189 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750()
274 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
346 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll()
357 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_set_pll()
377 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_set_ssc()
378 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
425 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); in gl9750_hw_setting()
[all …]
A Dsdhci-sprd.c113 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
187 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
232 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
245 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
251 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
258 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
264 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), in sdhci_sprd_enable_phy_dll()
269 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), in sdhci_sprd_enable_phy_dll()
270 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); in sdhci_sprd_enable_phy_dll()
670 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_sprd_probe()
[all …]
A Dsdhci-pci-dwc-mshc.c39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
A Dsdhci-milbeaut.c65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
149 val = sdhci_readl(host, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
196 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_vendor_init()
A Dsdhci-brcmstb.c107 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
109 sdhci_readl(host, SDHCI_BUFFER); in sdhci_brcmstb_cqe_enable()
110 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
289 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_brcmstb_probe()
292 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_brcmstb_probe()
A Dsdhci-tegra.c346 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
424 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
442 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
487 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl()
551 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
569 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
827 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); in tegra_sdhci_hs400_dll_cal()
864 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_tap_correction()
935 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_post_tuning()
1028 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_set_uhs_signaling()
[all …]
A Dsdhci-pci-o2micro.c83 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
105 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
139 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
151 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
170 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
250 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
569 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
584 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
620 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
A Dsdhci.c59 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs()
65 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs()
68 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs()
78 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs()
80 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs()
86 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs()
90 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs()
92 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs()
95 sdhci_readl(host, SDHCI_RESPONSE + 8), in sdhci_dumpregs()
103 sdhci_readl(host, SDHCI_ADMA_ERROR), in sdhci_dumpregs()
[all …]
A Dsdhci-of-sparx5.c236 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION)); in sdhci_sparx5_probe()
238 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); in sdhci_sparx5_probe()
A Dsdhci-of-dwcmshc.c166 vendor = sdhci_readl(host, reg); in dwcmshc_hs400_enhanced_strobe()
210 extra = sdhci_readl(host, reg); in dwcmshc_rk3568_set_clock()
400 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; in dwcmshc_probe()
A Dsdhci-of-arasan.c354 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
433 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
435 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable()
436 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
811 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
878 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
A Dsdhci-of-at91.c121 u32 calcr = sdhci_readl(host, SDMMC_CALCR); in sdhci_at91_reset()
126 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), in sdhci_at91_reset()
A Dsdhci-pxav3.c129 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in armada_38x_quirks()
130 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in armada_38x_quirks()
A Dsdhci-acpi.c379 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot()
380 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot()
1004 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
A Dsdhci-esdhc-imx.c924 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
951 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
1479 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
1481 sdhci_readl(host, SDHCI_BUFFER); in esdhc_cqe_enable()
1482 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
A Dsdhci.h689 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
730 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
A Dsdhci-pci-core.c629 val = sdhci_readl(host, INTEL_HS400_ES_REG); in intel_hs400_enhanced_strobe()
980 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); in glk_rpm_retune_wa()
981 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); in glk_rpm_retune_wa()
1736 return sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_read_present_state()
A Dsdhci-of-aspeed.c102 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); in aspeed_sdc_set_slot_capability()
A Dsdhci-msm.c2082 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE); in sdhci_msm_cqe_disable()
/linux/
A DSystem.map45768 ffff800010c4e770 t sdhci_readl
46219 ffff800010c766b4 t sdhci_readl

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