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Searched refs:tegra_dc_writel (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/tegra/
A Ddc.c48 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
50 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
1588 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1675 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1687 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1731 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
2030 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2044 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2050 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2071 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
[all …]
A Drgb.c85 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
106 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
112 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
117 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
121 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_rgb_encoder_enable()
A Dhub.c107 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
198 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
218 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
290 tegra_dc_writel(dc, value, offset); in tegra_shared_plane_set_owner()
889 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
893 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
895 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
897 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
A Dhdmi.c1145 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1217 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_enable()
1219 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, in tegra_hdmi_encoder_enable()
1225 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_enable()
1229 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_enable()
1232 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_enable()
1376 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()
A Dsor.c2232 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2457 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2464 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2554 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2584 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2629 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2926 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
A Ddc.h116 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, in tegra_dc_writel() function
A Ddsi.c861 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()

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