| /linux/Documentation/userspace-api/media/v4l/ |
| A D | pixfmt-yuv-planar.rst | 102 - 64x32 tiles
111 - 16x16 tiles
271 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
276 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
281 tiles is stored in linear order. The layouts of the luma and chroma
284 ``V4L2_PIX_FMT_NV12_4L4`` stores pixel in 4x4 tiles, and stores
285 tiles linearly in memory. The line stride and image height must be
289 ``V4L2_PIX_FMT_NV12_16L16`` stores pixel in 16x16 tiles, and stores
290 tiles linearly in memory. The line stride and image height must be
295 tiles linearly in memory. The line stride and image height must be
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| A D | nv25.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
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| A D | nv35.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
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| A D | nv36.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
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| A D | nv40.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
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| A D | nv20.c | 46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
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| A D | nv30.c | 52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
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| /linux/Documentation/devicetree/bindings/arm/ |
| A D | arm,integrator.yaml | 14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
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| A D | arm,vexpress-juno.yaml | 18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
130 description: When describing tiles consisting of more than one DCC, its
139 the connection between the motherboard and any tiles. Sometimes the
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| A D | l2c2x0.yaml | 179 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_fb.c | 394 unsigned int tiles; in intel_adjust_tile_offset() local
400 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
402 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
403 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
493 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
508 tiles = *x / tile_width; in intel_compute_aligned_offset()
511 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
937 unsigned int tiles; in calc_plane_normal_size() local
944 tiles = DIV_ROUND_UP(size, intel_tile_size(i915)); in calc_plane_normal_size()
953 tiles++; in calc_plane_normal_size()
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| /linux/Documentation/admin-guide/perf/ |
| A D | thunderx2-pmu.rst | 9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
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| /linux/drivers/pinctrl/qcom/ |
| A D | pinctrl-msm.h | 132 const char *const *tiles; member
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| A D | pinctrl-msm.c | 1413 if (soc_data->tiles) { in msm_pinctrl_probe()
1416 soc_data->tiles[i]); in msm_pinctrl_probe()
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| A D | pinctrl-sc8180x.c | 1600 .tiles = sc8180x_tiles,
1614 .tiles = sc8180x_tiles,
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| /linux/arch/arm/include/debug/ |
| A D | vexpress.S | 28 @ - all other (RS1 complaint) tiles use UART mapped
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| /linux/Documentation/ABI/testing/ |
| A D | sysfs-driver-hid-picolcd | 41 tiles get changed and it's not appropriate to expect the application
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| /linux/arch/arm/mach-vexpress/ |
| A D | Kconfig | 25 ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
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| /linux/arch/arm/boot/dts/ |
| A D | arm-realview-eb.dts | 42 * core tiles.
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | arm,syscon-icst.yaml | 30 In the core modules and logic tiles, the ICST is a configurable clock fed
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| A D | qcom,qcs404-pinctrl.txt | 15 tiles.
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| A D | qcom,sc7180-pinctrl.txt | 15 TLMM tiles
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| A D | qcom,sm8150-pinctrl.txt | 15 and east TLMM tiles.
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| A D | qcom,sdm660-pinctrl.txt | 16 TLMM tiles.
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| /linux/arch/arm/ |
| A D | Kconfig.debug | 1325 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
1332 Note that this will only work with standard A-class core tiles,
1344 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
1349 of the tiles using the RS1 memory map, including all new A-class
1350 core tiles, FPGA-based SMMs and software models.
1353 bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
1358 Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
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