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Searched refs:train_set (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c431 intel_dp->train_set[lane] = in intel_dp_get_adjust_train()
451 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
505 #define TRAIN_SET_VSWING_ARGS(train_set) \ argument
506 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \
507 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \
508 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \
509 _TRAIN_SET_VSWING_ARGS((train_set)[3])
517 _TRAIN_SET_PREEMPH_ARGS((train_set)[3])
520 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ argument
524 _TRAIN_SET_TX_FFE_ARGS((train_set)[3])
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A Dg4x_dp.c817 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
819 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
903 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
905 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
980 static u32 g4x_signal_levels(u8 train_set) in g4x_signal_levels() argument
999 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in g4x_signal_levels()
1023 u8 train_set = intel_dp->train_set[0]; in g4x_set_signal_levels() local
1026 signal_levels = g4x_signal_levels(train_set); in g4x_set_signal_levels()
1039 static u32 snb_cpu_edp_signal_levels(u8 train_set) in snb_cpu_edp_signal_levels() argument
1071 u8 train_set = intel_dp->train_set[0]; in snb_cpu_edp_set_signal_levels() local
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A Dintel_ddi.c1342 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level() local
1345 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; in intel_ddi_dp_level()
1347 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
A Dintel_display_types.h1579 u8 train_set[4]; member
A Dintel_dp.c1862 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
3459 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
A Dintel_display_debugfs.c1549 intel_dp->train_set[0]); in i915_displayport_test_data_show()
/linux/drivers/gpu/drm/amd/amdgpu/
A Datombios_dp.c204 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
236 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
495 u8 train_set[4]; member
511 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
605 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
650 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
659 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_cr()
660 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()
701 dp_info->train_set); in amdgpu_atombios_dp_link_train_ce()
712 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_ce()
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/linux/drivers/gpu/drm/radeon/
A Datombios_dp.c259 u8 train_set[4]) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
546 u8 train_set[4]; member
562 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
673 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
697 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
714 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
726 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_cr()
727 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()
777 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_ce()
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/linux/drivers/gpu/drm/xlnx/
A Dzynqmp_dp.c320 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
614 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
636 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
654 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
662 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
720 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
725 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
733 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
863 memset(dp->train_set, 0, sizeof(dp->train_set)); in zynqmp_dp_train()
/linux/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c271 uint8_t train_set[4]; member
1302 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1391 intel_dp->train_set, in cdv_intel_dplink_set_level()
1396 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1496 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1507 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1514 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1535 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1547 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
1580 intel_dp->train_set[0], in cdv_intel_dp_complete_link_train()
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