Searched refs:uhs (Results 1 – 25 of 117) sorted by relevance
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| /linux/arch/arm/boot/dts/ |
| A D | imx6qdl-colibri-v1_1-uhs.dtsi | 40 sd-uhs-sdr12;
41 sd-uhs-sdr25;
42 sd-uhs-sdr50;
43 sd-uhs-sdr104;
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| A D | rk3288-veyron-sdmmc.dtsi | 83 sd-uhs-sdr12;
84 sd-uhs-sdr25;
85 sd-uhs-sdr50;
86 sd-uhs-sdr104;
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| A D | stih410-b2120.dts | 31 sd-uhs-sdr50;
32 sd-uhs-sdr104;
33 sd-uhs-ddr50;
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| A D | imx6ull-colibri-eval-v3.dtsi | 173 sd-uhs-sdr12;
174 sd-uhs-sdr25;
175 sd-uhs-sdr50;
176 sd-uhs-sdr104;
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| A D | stih418-b2199.dts | 81 sd-uhs-sdr50;
82 sd-uhs-sdr104;
83 sd-uhs-ddr50;
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| A D | rk3288-phycore-rdk.dts | 231 sd-uhs-sdr12;
232 sd-uhs-sdr25;
233 sd-uhs-sdr50;
234 sd-uhs-sdr104;
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| /linux/arch/riscv/boot/dts/microchip/ |
| A D | microchip-mpfs-icicle-kit.dts | 61 sd-uhs-sdr12;
62 sd-uhs-sdr25;
63 sd-uhs-sdr50;
64 sd-uhs-sdr104;
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| /linux/arch/arm64/boot/dts/freescale/ |
| A D | fsl-ls1012a-rdb.dts | 29 sd-uhs-sdr104;
30 sd-uhs-sdr50;
31 sd-uhs-sdr25;
32 sd-uhs-sdr12;
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| A D | fsl-lx2160a-clearfog-itx.dtsi | 88 sd-uhs-sdr104;
89 sd-uhs-sdr50;
90 sd-uhs-sdr25;
91 sd-uhs-sdr12;
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| A D | fsl-ls1046a-rdb.dts | 41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
43 sd-uhs-sdr25;
44 sd-uhs-sdr12;
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| A D | fsl-lx2160a-rdb.dts | 113 sd-uhs-sdr104;
114 sd-uhs-sdr50;
115 sd-uhs-sdr25;
116 sd-uhs-sdr12;
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| A D | fsl-ls1028a-rdb.dts | 106 sd-uhs-sdr104;
107 sd-uhs-sdr50;
108 sd-uhs-sdr25;
109 sd-uhs-sdr12;
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| A D | fsl-ls1028a-kontron-sl28.dts | 99 sd-uhs-sdr104;
100 sd-uhs-sdr50;
101 sd-uhs-sdr25;
102 sd-uhs-sdr12;
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| /linux/Documentation/devicetree/bindings/mmc/ |
| A D | socionext,uniphier-sd.yaml | 88 pinctrl-names = "default", "uhs";
98 sd-uhs-sdr12;
99 sd-uhs-sdr25;
100 sd-uhs-sdr50;
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| A D | sdhci-st.txt | 51 - sd-uhs-sdr50: To enable the SDR50 in the mmcss.
54 - sd-uhs-sdr104: To enable the SDR104 in the mmcss.
57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
107 sd-uhs-sdr50;
108 sd-uhs-sdr104;
109 sd-uhs-ddr50;
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| A D | brcm,sdhci-brcmstb.txt | 21 sd-uhs-sdr50;
22 sd-uhs-ddr50;
23 sd-uhs-sdr104;
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| A D | sdhci-sprd.txt | 24 - pinctrl-1: should contain uhs mode pin control
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
60 sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
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| A D | cdns,sdhci.yaml | 50 cdns,phy-input-delay-sd-uhs-sdr12:
56 cdns,phy-input-delay-sd-uhs-sdr25:
62 cdns,phy-input-delay-sd-uhs-sdr50:
68 cdns,phy-input-delay-sd-uhs-ddr50:
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| /linux/drivers/mmc/host/ |
| A D | sdhci-pxav3.c | 240 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) in pxav3_set_uhs_signaling() argument
254 switch (uhs) { in pxav3_set_uhs_signaling()
280 if (uhs == MMC_TIMING_UHS_SDR50 || in pxav3_set_uhs_signaling()
281 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
284 } else if (uhs == MMC_TIMING_MMC_HS) { in pxav3_set_uhs_signaling()
297 __func__, uhs, ctrl_2); in pxav3_set_uhs_signaling()
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| A D | sdhci-st.c | 257 unsigned int uhs) in sdhci_st_set_uhs_signaling() argument
266 switch (uhs) { in sdhci_st_set_uhs_signaling()
300 "(uhs %d)\n", uhs); in sdhci_st_set_uhs_signaling()
302 dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2); in sdhci_st_set_uhs_signaling()
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| /linux/arch/arm64/boot/dts/amlogic/ |
| A D | meson-gxl-s905x-libretech-cc-v2.dts | 248 sd-uhs-sdr12;
249 sd-uhs-sdr25;
250 sd-uhs-sdr50;
251 sd-uhs-ddr50;
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| A D | meson-gxbb-p20x.dtsi | 196 sd-uhs-sdr12;
197 sd-uhs-sdr25;
198 sd-uhs-sdr50;
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8183-pumpkin.dts | 154 sd-uhs-sdr50;
155 sd-uhs-sdr104;
258 mmc0_pins_uhs: mmc0-pins-uhs {
316 mmc1_pins_uhs: mmc1-pins-uhs {
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| /linux/arch/arm64/boot/dts/rockchip/ |
| A D | rk3308-roc-cc.dts | 181 sd-uhs-sdr25;
182 sd-uhs-sdr50;
183 sd-uhs-sdr104;
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| A D | rk3328-nanopi-r2s.dts | 354 sd-uhs-sdr12;
355 sd-uhs-sdr25;
356 sd-uhs-sdr50;
357 sd-uhs-sdr104;
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Completed in 29 milliseconds
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