Home
last modified time | relevance | path

Searched refs:ull (Results 1 – 25 of 73) sorted by relevance

123

/linux/drivers/clk/imx/
A Dclk-pllv1.c57 unsigned long long ull; in clk_pllv1_recalc_rate() local
99 ull = (unsigned long long)rate * mfn_abs; in clk_pllv1_recalc_rate()
101 do_div(ull, mfd + 1); in clk_pllv1_recalc_rate()
104 ull = (rate * mfi) - ull; in clk_pllv1_recalc_rate()
106 ull = (rate * mfi) + ull; in clk_pllv1_recalc_rate()
108 return ull; in clk_pllv1_recalc_rate()
/linux/arch/parisc/lib/
A Ducmpdi2.c5 unsigned long long ull; member
14 union ull_union au = {.ull = a}; in __ucmpdi2()
15 union ull_union bu = {.ull = b}; in __ucmpdi2()
/linux/arch/x86/kvm/mmu/
A Dspte.c309 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; in kvm_mmu_set_ept_masks()
310 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; in kvm_mmu_set_ept_masks()
311 shadow_nx_mask = 0ull; in kvm_mmu_set_ept_masks()
313 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK; in kvm_mmu_set_ept_masks()
315 shadow_me_mask = 0ull; in kvm_mmu_set_ept_masks()
/linux/drivers/crypto/cavium/zip/
A Dzip_main.c155 que_sbuf_ctl.u_reg64 = 0ull; in zip_init_hw()
184 que_sbuf_addr.u_reg64 = 0ull; in zip_init_hw()
218 que_map.u_reg64 = 0ull; in zip_init_hw()
228 que_pri.u_reg64 = 0ull; in zip_init_hw()
459 u64 val = 0ull; in zip_stats_show()
460 u64 avg_chunk = 0ull, avg_cr = 0ull; in zip_stats_show()
A Dzip_device.c133 ncp.u_reg64 = 0ull; in zip_load_instr()
158 dbell.u_reg64 = 0ull; in zip_load_instr()
/linux/tools/testing/selftests/bpf/progs/
A Dbpf_cubic.c130 if (!(x & (~0ull << (BITS_PER_U64-32)))) { in fls64()
134 if (!(x & (~0ull << (BITS_PER_U64-16)))) { in fls64()
138 if (!(x & (~0ull << (BITS_PER_U64-8)))) { in fls64()
142 if (!(x & (~0ull << (BITS_PER_U64-4)))) { in fls64()
146 if (!(x & (~0ull << (BITS_PER_U64-2)))) { in fls64()
150 if (!(x & (~0ull << (BITS_PER_U64-1)))) in fls64()
/linux/arch/powerpc/include/asm/
A Dspu.h379 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
383 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
579 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
580 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
585 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
630 #define SPU_ECC_CNTL_E (1ull << 0ull)
/linux/drivers/crypto/cavium/cpt/
A Dcptpf_main.c94 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull); in cpt_disable_mbox_interrupts()
100 cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); in cpt_disable_ecc_interrupts()
106 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); in cpt_disable_exec_interrupts()
119 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull); in cpt_enable_mbox_interrupts()
425 CPTX_PF_ENGX_UCODE_BASE(0, core), 0ull); in cpt_unload_microcode()
A Dcptpf_mbox.c23 mbx->data = 0ull; in cpt_mbox_send_ack()
/linux/arch/mips/include/asm/octeon/
A Dcvmx-pip.h47 CVMX_PIP_L4_NO_ERR = 0ull,
78 CVMX_PIP_IP_NO_ERR = 0ull,
102 CVMX_PIP_RX_NO_ERR = 0ull,
A Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
/linux/drivers/infiniband/core/
A Dpacker.c101 mask = cpu_to_be64((~0ull >> (64 - desc[i].size_bits)) << shift); in ib_pack()
180 mask = (~0ull >> (64 - desc[i].size_bits)) << shift; in ib_unpack()
/linux/drivers/misc/cxl/
A Dcxllib.c13 #define CXL_INVALID_DRA ~0ull
67 (~0ull << CXL_DUMMY_READ_ALIGN); in allocate_dummy_read_buf()
/linux/fs/ocfs2/
A Docfs2_trace.h306 TP_ARGS(ull, value1, value2, value3),
308 __field( unsigned long long, ull )
314 __entry->ull = ull;
320 __entry->ull, __entry->value1,
328 TP_ARGS(ull, value1, value2, value3))
333 TP_ARGS(ull, value1, value2, value3),
335 __field(unsigned long long, ull)
341 __entry->ull = ull;
347 __entry->ull, __entry->value1,
355 TP_ARGS(ull, value1, value2, value3))
[all …]
/linux/arch/x86/include/asm/
A Dprocessor-flags.h48 #define CR3_PCID_MASK 0ull
A Dpgtable-invert.h24 return __pte_needs_invert(val) ? ~0ull : 0; in protnone_mask()
/linux/drivers/crypto/marvell/octeontx/
A Dotx_cptpf_mbox.c89 mbx->data = 0ull; in otx_cpt_mbox_send_ack()
98 mbx->data = 0ull; in otx_cptpf_mbox_send_nack()
A Dotx_cptpf_main.c20 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0)); in otx_cpt_disable_mbox_interrupts()
26 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0)); in otx_cpt_enable_mbox_interrupts()
/linux/arch/powerpc/platforms/cell/spufs/
A Dspu_utils.h15 unsigned long long ull; member
/linux/arch/x86/hyperv/
A Dhv_init.c33 u64 hv_current_partition_id = ~0ull;
488 BUG_ON(hv_root_partition && hv_current_partition_id == ~0ull); in hyperv_init()
/linux/arch/powerpc/mm/
A Dinit-common.c24 phys_addr_t memstart_addr __ro_after_init = (phys_addr_t)~0ull;
/linux/include/linux/
A Dbitfield.h52 BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
/linux/include/linux/ceph/
A Dmsgr.h33 #define CEPH_MSGR2_INCARNATION_1 (0ull)
A Dceph_features.h10 #define CEPH_FEATURE_INCARNATION_1 (0ull)
/linux/drivers/infiniband/hw/hfi1/
A Dchip.c114 #define LRH_BTH_QW 0ull
123 #define LRH_SC_QW 0ull
128 #define LRH_SC_VALUE 0ull
157 #define L2_TYPE_QW 0ull
166 #define L4_TYPE_BIT_OFFSET 0ull
635 /* 0*/ FLAG_ENTRY0("Reserved", 0ull),
6803 freeze ? ALL_FROZE : 0ull); in wait_for_freeze_status()
13637 write_csr(dd, CCE_ERR_CLEAR, ~0ull); in reset_cce_csrs()
14643 write_csr(dd, RCV_ERR_MASK, ~0ull); in init_rxe()
14681 write_csr(dd, CCE_ERR_MASK, ~0ull); in init_other()
[all …]

Completed in 71 milliseconds

123