Home
last modified time | relevance | path

Searched refs:wave (Results 1 – 20 of 20) sorted by relevance

/linux/sound/pci/
A Dad1889.c90 struct ad1889_register_state wave; member
190 chip->wave.reg = reg; in ad1889_channel_reset()
358 chip->wave.size = size; in snd_ad1889_playback_prepare()
359 chip->wave.reg = reg; in snd_ad1889_playback_prepare()
360 chip->wave.addr = rt->dma_addr; in snd_ad1889_playback_prepare()
362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); in snd_ad1889_playback_prepare()
379 chip->wave.addr, count, size, reg, rt->rate); in snd_ad1889_playback_prepare()
460 chip->wave.reg = wsmc; in snd_ad1889_playback_trigger()
516 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) in snd_ad1889_playback_pointer()
520 ptr -= chip->wave.addr; in snd_ad1889_playback_pointer()
[all …]
/linux/sound/pci/emu10k1/
A Demu10k1.c91 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local
165 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe()
166 wave == NULL) { in snd_card_emu10k1_probe()
171 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe()
172 strcpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
/linux/sound/pci/au88x0/
A Dau88x0.c267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in snd_vortex_probe()
268 || wave == NULL) { in snd_vortex_probe()
273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_vortex_probe()
274 strcpy(wave->name, "Aureal Synth"); in snd_vortex_probe()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_wait_for_waves_assigned()
469 if (((1 << wave) & mask) && in gfx_v9_4_2_wait_for_waves_assigned()
1829 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1840 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1852 wave = i % cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1858 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_2_log_cu_timeout_status()
1860 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
A Dgfx_v6_0.c2986 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2994 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2998 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v6_0_read_wave_data()
3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v6_0_read_wave_data()
3030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v6_0_read_wave_data()
3034 uint32_t wave, uint32_t start, in gfx_v6_0_read_wave_sgprs() argument
[all …]
A Damdgpu_gfx.h226 uint32_t wave, uint32_t *dst, int *no_fields);
228 uint32_t wave, uint32_t thread, uint32_t start,
231 uint32_t wave, uint32_t start, uint32_t size,
A Dgfx_v7_0.c4161 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4169 uint32_t wave, uint32_t thread, in wave_read_regs() argument
4173 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4187 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4188 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4189 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4192 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v7_0_read_wave_data()
4204 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v7_0_read_wave_data()
4205 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v7_0_read_wave_data()
4209 uint32_t wave, uint32_t start, in gfx_v7_0_read_wave_sgprs() argument
[all …]
A Damdgpu_debugfs.c891 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
901 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
922 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
983 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
993 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read()
1016 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1019 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
A Dgfx_v8_0.c5238 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5246 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5250 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v8_0_read_wave_data()
5281 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v8_0_read_wave_data()
5282 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v8_0_read_wave_data()
5286 uint32_t wave, uint32_t start, in gfx_v8_0_read_wave_sgprs() argument
[all …]
A Dgfx_v9_0.c2063 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2071 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2075 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
2090 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
2091 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
2102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v9_0_read_wave_data()
2103 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v9_0_read_wave_data()
2107 uint32_t wave, uint32_t start, in gfx_v9_0_read_wave_sgprs() argument
2111 adev, simd, wave, 0, in gfx_v9_0_read_wave_sgprs()
2116 uint32_t wave, uint32_t thread, in gfx_v9_0_read_wave_vgprs() argument
[all …]
A Dgfx_v10_0.c4560 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4570 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4587 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
4588 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
4589 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
4601 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); in gfx_v10_0_read_wave_data()
4602 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); in gfx_v10_0_read_wave_data()
4606 uint32_t wave, uint32_t start, in gfx_v10_0_read_wave_sgprs() argument
4612 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, in gfx_v10_0_read_wave_sgprs()
4617 uint32_t wave, uint32_t thread, in gfx_v10_0_read_wave_vgprs() argument
[all …]
/linux/Documentation/devicetree/bindings/rtc/
A Dmaxim,ds3231.txt14 - 0: square-wave output on the SQW pin
15 - 1: square-wave output on the 32kHz pin
A Dnxp,pcf85063.txt17 - clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
A Drtc-m41t80.txt25 - clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
A Dpll.txt18 - ti,clkmode-square-wave: Indicates that the the board is supplying a square
19 wave input on the OSCIN pin instead of using a crystal oscillator.
61 ti,clkmode-square-wave;
/linux/drivers/gpu/ipu-v3/
A Dipu-dc.c120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
/linux/Documentation/devicetree/bindings/clock/
A Dnvidia,tegra124-dfll.txt56 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
/linux/Documentation/virt/kvm/
A Dtimekeeping.rst103 This generates a high / low square wave. The count
112 which generates sine-like tones by low-pass filtering the square wave output.
253 bit 3 = Square wave interrupt enable
/linux/drivers/media/rc/
A DKconfig374 wave and pulses.
/linux/Documentation/driver-api/media/drivers/
A Dvidtv.rst34 Elementary Stream, which in turn contains a SMPTE 302m encoded sine-wave.

Completed in 79 milliseconds