| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_ih.c | 75 unsigned wptr_offs, rptr_offs; in amdgpu_ih_ring_init() local
77 r = amdgpu_device_wb_get(adev, &wptr_offs); in amdgpu_ih_ring_init()
83 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
93 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
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| A D | amdgpu_ring.c | 206 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); in amdgpu_ring_init()
293 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); in amdgpu_ring_fini()
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| A D | jpeg_v3_0.c | 425 return adev->wb.wb[ring->wptr_offs]; in jpeg_v3_0_dec_ring_get_wptr()
442 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v3_0_dec_ring_set_wptr()
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| A D | vcn_v2_0.c | 1333 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_dec_ring_get_wptr()
1354 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1562 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1567 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1586 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1593 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
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| A D | vcn_v2_5.c | 1488 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_dec_ring_get_wptr()
1505 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1602 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1607 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1626 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
1633 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
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| A D | sdma_v5_2.c | 263 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_2_ring_get_wptr()
292 ring->wptr_offs, in sdma_v5_2_ring_set_wptr()
296 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
297 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
633 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_2_gfx_resume()
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| A D | sdma_v4_0.c | 745 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()
771 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_ring_set_wptr()
777 ring->wptr_offs, in sdma_v4_0_ring_set_wptr()
814 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_page_ring_get_wptr()
836 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_page_ring_set_wptr()
1228 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
1319 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_page_resume()
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| A D | jpeg_v2_5.c | 402 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_5_dec_ring_get_wptr()
419 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_5_dec_ring_set_wptr()
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| A D | sdma_v3_0.c | 370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; in sdma_v3_0_ring_get_wptr()
390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
718 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v3_0_gfx_resume()
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| A D | mes_v10_1.c | 49 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], in mes_v10_1_ring_set_wptr()
68 &ring->adev->wb.wb[ring->wptr_offs]); in mes_v10_1_ring_get_wptr()
682 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in mes_v10_1_mqd_init()
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| A D | jpeg_v2_0.c | 410 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_0_dec_ring_get_wptr()
427 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
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| A D | sdma_v5_0.c | 376 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_0_ring_get_wptr()
405 ring->wptr_offs, in sdma_v5_0_ring_set_wptr()
409 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
410 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
752 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_0_gfx_resume()
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| A D | vcn_v3_0.c | 1684 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_dec_ring_get_wptr()
1710 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_dec_ring_set_wptr()
1996 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
2001 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
2020 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
2027 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
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| A D | vce_v4_0.c | 86 return adev->wb.wb[ring->wptr_offs]; in vce_v4_0_ring_get_wptr()
109 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
180 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
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| A D | amdgpu_ring.h | 238 unsigned wptr_offs; member
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| A D | uvd_v7_0.c | 120 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()
155 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
756 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; in uvd_v7_0_mmsch_start()
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| A D | gfx_v9_0.c | 854 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_kiq_map_queues()
3360 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_cp_gfx_resume()
3578 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()
3860 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v9_0_kcq_init_queue()
5324 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_gfx()
5339 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
5513 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_compute()
5525 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
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| A D | gfx_v8_0.c | 4313 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_gfx_resume()
4396 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_kiq_kcq_enable()
4526 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()
6063 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()
6074 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_gfx()
6274 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()
6282 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_compute()
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| A D | gfx_v10_0.c | 3609 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx10_kiq_map_queues()
6382 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
6419 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
6643 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_gfx_mqd_init()
6757 adev->wb.wb[ring->wptr_offs] = 0; in gfx_v10_0_gfx_init_queue()
6937 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_compute_mqd_init()
7157 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v10_0_kcq_init_queue()
8498 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_gfx()
8513 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v10_0_ring_set_wptr_gfx()
8532 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_compute()
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| A D | gfx_v7_0.c | 2680 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
2688 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
2984 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
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| /linux/drivers/gpu/drm/radeon/ |
| A D | cik.c | 4164 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4180 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
8413 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8425 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
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| A D | radeon.h | 860 unsigned wptr_offs; member
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