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Searched refs:_parents (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/clk/sprd/
A Dmux.h39 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \ argument
46 .hw.init = _fn(_name, _parents, \
51 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \ argument
53 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
59 SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
62 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \ argument
64 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
70 SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
/linux/drivers/clk/mediatek/
A Dclk-mux.h40 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
53 .parent_names = _parents, \
54 .num_parents = ARRAY_SIZE(_parents), \
62 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
65 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
70 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
73 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
78 #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
81 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
A Dclk-mtk.h82 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
92 .parent_names = _parents, \
93 .num_parents = ARRAY_SIZE(_parents), \
102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
104 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
112 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
116 MUX_FLAGS(_id, _name, _parents, _reg, \
127 .parent_names = _parents, \
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/linux/drivers/clk/tegra/
A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
157 _parents##_idx, 0, _lock)
163 _parents##_idx, 0, NULL)
170 _clk_id, _parents##_idx, 0, NULL)
184 _clk_id, _parents##_idx, 0, NULL)
191 _parents##_idx, 0, NULL)
198 _parents##_idx, 0, NULL)
200 #define I2C(_name, _parents, _offset,\ argument
205 _parents##_idx, 0, NULL)
212 _clk_id, _parents##_idx, 0, NULL)
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A Dclk-tegra30.c155 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
157 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
161 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
163 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
167 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
169 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
174 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
177 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
A Dclk-tegra20.c133 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
135 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
140 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
142 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
147 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
150 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
A Dclk-tegra124.c97 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
98 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
101 _parents##_idx, 0, _lock)
103 #define NODIV(_name, _parents, _offset, \ argument
106 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
109 _clk_id, _parents##_idx, 0, _lock)
A Dclk-tegra114.c115 #define MUX8(_name, _parents, _offset, \ argument
117 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
119 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
/linux/drivers/clk/sunxi-ng/
A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
49 _parents, \
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
68 _parents, \
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
79 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
103 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
114 _parents, \
A Dccu_mux.h49 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
58 _parents, \
64 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
66 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
72 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
A Dccu_div.h112 _parents, _table, \ argument
124 _parents, \
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
134 _parents, NULL, \
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
143 _parents, NULL, \
A Dccu_nkm.h34 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
50 _parents, \
/linux/drivers/clk/pxa/
A Dclk-pxa.h18 static const char *const name ## _parents[] __initconst
32 name ## _parents, \
33 ARRAY_SIZE(name ## _parents), \
47 name ## _parents, \
48 ARRAY_SIZE(name ## _parents), \
64 name ## _parents, \
65 ARRAY_SIZE(name ## _parents), \
81 name ## _parents, \
82 ARRAY_SIZE(name ## _parents), \
/linux/drivers/clk/actions/
A Dowl-mux.h34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
41 _parents, \
/linux/drivers/clk/
A Dclk-oxnas.c89 #define OXNAS_GATE(_name, _bit, _parents) \ argument
95 .parent_names = _parents, \
96 .num_parents = ARRAY_SIZE(_parents), \
A Dclk-stm32h7.c567 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\ argument
570 .parents = _parents,\
571 .num_parents = ARRAY_SIZE(_parents),\
578 #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\ argument
579 M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, 0)\
1178 #define M_MCO_F(_name, _parents, _mux_offset, _mux_shift, _mux_width,\ argument
1186 .parent_name = _parents,\
1187 .num_parents = ARRAY_SIZE(_parents),\
A Dclk-stm32mp1.c1203 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1207 .parent_names = _parents,\
1208 .num_parents = ARRAY_SIZE(_parents),\
1219 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ argument
1223 .parent_names = _parents,\
1224 .num_parents = ARRAY_SIZE(_parents),\
1339 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1343 .parent_names = _parents,\
1344 .num_parents = ARRAY_SIZE(_parents),\
1357 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ argument
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A Dclk-bm1880.c160 #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ argument
163 .parents = _parents, \
164 .num_parents = ARRAY_SIZE(_parents), \
/linux/include/linux/
A Dclk-provider.h1301 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
1305 .parent_names = _parents, \
1306 .num_parents = ARRAY_SIZE(_parents), \
1310 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ argument
1314 .parent_hws = _parents, \
1315 .num_parents = ARRAY_SIZE(_parents), \
1319 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ argument
1323 .parent_data = _parents, \
1324 .num_parents = ARRAY_SIZE(_parents), \
A Dsh_clk.h175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
182 .parent_table = _parents, \
/linux/drivers/clk/qcom/
A Dlcc-mdm9615.c230 static const char * const lcc_##prefix##_parents[] = { \
243 .parent_names = lcc_##prefix##_parents, \
258 .parent_names = lcc_##prefix##_parents, \
A Dlcc-msm8960.c228 static const char * const lcc_##prefix##_parents[] = { \
241 .parent_names = lcc_##prefix##_parents, \
256 .parent_names = lcc_##prefix##_parents, \
/linux/drivers/clk/meson/
A Daxg-audio.c319 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ argument
320 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \

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