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Searched refs:iobase (Results 1 – 25 of 297) sorted by relevance

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/linux/drivers/staging/vt6655/
A Dmac.h697 #define MACvClearISR(iobase) \ argument
700 #define MACvStart(iobase) \ argument
716 #define MACvRxOn(iobase) \ argument
719 #define MACvReceive0(iobase) \ argument
729 #define MACvReceive1(iobase) \ argument
739 #define MACvTxOn(iobase) \ argument
742 #define MACvTransmit0(iobase) \ argument
752 #define MACvTransmitAC0(iobase) \ argument
802 #define MACvIntDisable(iobase) \ argument
805 #define MACvSelectPage0(iobase) \ argument
[all …]
A Dsrom.c60 unsigned char SROMbyReadEmbedded(void __iomem *iobase, in SROMbyReadEmbedded() argument
69 VNSvInPortB(iobase + MAC_REG_I2MCFG, &byOrg); in SROMbyReadEmbedded()
73 VNSvOutPortB(iobase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID); in SROMbyReadEmbedded()
74 VNSvOutPortB(iobase + MAC_REG_I2MTGAD, byContntOffset); in SROMbyReadEmbedded()
77 VNSvOutPortB(iobase + MAC_REG_I2MCSR, I2MCSR_EEMR); in SROMbyReadEmbedded()
80 VNSvInPortB(iobase + MAC_REG_I2MCSR, &byWait); in SROMbyReadEmbedded()
90 VNSvInPortB(iobase + MAC_REG_I2MDIPT, &byData); in SROMbyReadEmbedded()
91 VNSvOutPortB(iobase + MAC_REG_I2MCFG, byOrg); in SROMbyReadEmbedded()
113 *pbyEepromRegs = SROMbyReadEmbedded(iobase, in SROMvReadAllContents()
131 void SROMvReadEtherAddress(void __iomem *iobase, in SROMvReadEtherAddress() argument
[all …]
/linux/drivers/comedi/drivers/
A Dni_atmio16d.c185 outw(0, dev->iobase + AD_CLEAR_REG); in reset_counters()
194 outw(0, dev->iobase + COM_REG_1); in reset_atmio16d()
195 outw(0, dev->iobase + COM_REG_2); in reset_atmio16d()
196 outw(0, dev->iobase + MUX_GAIN_REG); in reset_atmio16d()
210 outw(0, dev->iobase + AD_CLEAR_REG); in reset_atmio16d()
211 outw(0, dev->iobase + INT2CLR_REG); in reset_atmio16d()
217 outw(2048, dev->iobase + DAC0_REG); in reset_atmio16d()
218 outw(2048, dev->iobase + DAC1_REG); in reset_atmio16d()
227 val = inw(dev->iobase + AD_FIFO_REG); in atmio16d_interrupt()
417 outw(0, dev->iobase + INT2CLR_REG); in atmio16d_ai_cmd()
[all …]
A Dadv_pci_dio.c401 unsigned long iobase = dev->iobase + reg; in pci_dio_insn_bits_dirq_b() local
403 data[1] = inb(iobase); in pci_dio_insn_bits_dirq_b()
414 unsigned long iobase = dev->iobase + reg; in pci_dio_insn_bits_di_b() local
416 data[1] = inb(iobase); in pci_dio_insn_bits_di_b()
433 unsigned long iobase = dev->iobase + reg; in pci_dio_insn_bits_di_w() local
435 data[1] = inw(iobase); in pci_dio_insn_bits_di_w()
448 unsigned long iobase = dev->iobase + reg; in pci_dio_insn_bits_do_b() local
451 outb(s->state & 0xff, iobase); in pci_dio_insn_bits_do_b()
471 unsigned long iobase = dev->iobase + reg; in pci_dio_insn_bits_do_w() local
474 outw(s->state & 0xffff, iobase); in pci_dio_insn_bits_do_w()
[all …]
A Daddi_apci_1564.c181 outl(0x0, dev->iobase + APCI1564_DO_REG); in apci1564_reset()
195 outl(0x0, iobase + APCI1564_COUNTER(0)); in apci1564_reset()
196 outl(0x0, iobase + APCI1564_COUNTER(1)); in apci1564_reset()
197 outl(0x0, iobase + APCI1564_COUNTER(2)); in apci1564_reset()
239 unsigned long iobase; in apci1564_interrupt() local
584 val = inl(iobase + ADDI_TCW_CTRL_REG); in apci1564_counter_insn_config()
587 outl(val, iobase + ADDI_TCW_CTRL_REG); in apci1564_counter_insn_config()
590 val = inl(iobase + ADDI_TCW_CTRL_REG); in apci1564_counter_insn_config()
592 outl(val, iobase + ADDI_TCW_CTRL_REG); in apci1564_counter_insn_config()
604 val = inl(iobase + ADDI_TCW_CTRL_REG); in apci1564_counter_insn_config()
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A Ddmm32at.c171 dev->iobase + DMM32AT_FIFO_CTRL_REG); in dmm32at_ai_set_chanspec()
183 val = inb(dev->iobase + DMM32AT_AI_LSB_REG); in dmm32at_ai_get_sample()
197 status = inb(dev->iobase + context); in dmm32at_ai_status()
351 outb(lo1, dev->iobase + DMM32AT_CLK1); in dmm32at_setaitimer()
355 outb(lo2, dev->iobase + DMM32AT_CLK2); in dmm32at_setaitimer()
356 outb(hi2, dev->iobase + DMM32AT_CLK2); in dmm32at_setaitimer()
361 dev->iobase + DMM32AT_INTCLK_REG); in dmm32at_setaitimer()
466 dev->iobase + DMM32AT_AO_MSB_REG); in dmm32at_ao_insn_write()
474 inb(dev->iobase + DMM32AT_AO_MSB_REG); in dmm32at_ao_insn_write()
489 outb(data, dev->iobase + regbase + port); in dmm32at_8255_io()
[all …]
A Dni_daq_700.c85 outb(s->state & 0xff, dev->iobase + DIO_W); in daq700_dio_insn_bits()
89 val |= inb(dev->iobase + DIO_R) << 8; in daq700_dio_insn_bits()
120 status = inb(dev->iobase + STA_R2); in daq700_ai_eoc()
123 status = inb(dev->iobase + STA_R1); in daq700_ai_eoc()
153 outb(chan | 0x80, dev->iobase + CMD_R1); in daq700_ai_rinsn()
164 inw(dev->iobase + ADFIFO_R); in daq700_ai_rinsn()
166 outb(0x32, dev->iobase + CMO_R); in daq700_ai_rinsn()
174 d = inw(dev->iobase + ADFIFO_R); in daq700_ai_rinsn()
198 unsigned long iobase = dev->iobase; in daq700_ai_config() local
201 outb(0x00, iobase + CMD_R2); /* clear all bits */ in daq700_ai_config()
[all …]
A Daddi_apci_3501.c147 dev->iobase + APCI3501_AO_DATA_REG); in apci3501_ao_insn_write()
185 val = inb(iobase + AMCC_OP_REG_MCSR_NVCMD); in apci3501_eeprom_wait()
202 apci3501_eeprom_wait(iobase); in apci3501_eeprom_readw()
204 apci3501_eeprom_wait(iobase); in apci3501_eeprom_readw()
208 apci3501_eeprom_wait(iobase); in apci3501_eeprom_readw()
210 iobase + AMCC_OP_REG_MCSR_NVDATA); in apci3501_eeprom_readw()
211 apci3501_eeprom_wait(iobase); in apci3501_eeprom_readw()
215 apci3501_eeprom_wait(iobase); in apci3501_eeprom_readw()
217 apci3501_eeprom_wait(iobase); in apci3501_eeprom_readw()
281 outl(0x0, dev->iobase + APCI3501_DO_REG); in apci3501_reset()
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A Dpcmmio.c189 unsigned long iobase = dev->iobase; in pcmmio_dio_write() local
211 unsigned long iobase = dev->iobase; in pcmmio_dio_read() local
223 val = inb(iobase + PCMMIO_PAGE_REG(0)); in pcmmio_dio_read()
535 unsigned long iobase = dev->iobase; in pcmmio_ai_insn_read() local
561 iobase += PCMMIO_AI_2ND_ADC_OFFSET; in pcmmio_ai_insn_read()
571 outb(cmd, iobase + PCMMIO_AI_CMD_REG); in pcmmio_ai_insn_read()
577 val = inb(iobase + PCMMIO_AI_LSB_REG); in pcmmio_ai_insn_read()
618 unsigned long iobase = dev->iobase; in pcmmio_ao_insn_write() local
632 iobase += PCMMIO_AO_2ND_DAC_OFFSET; in pcmmio_ao_insn_write()
639 outb(0, iobase + PCMMIO_AO_MSB_REG); in pcmmio_ao_insn_write()
[all …]
A Dquatech_daqp_cs.c191 outb(0, dev->iobase + DAQP_CTRL_REG); in daqp_ai_cancel()
192 inb(dev->iobase + DAQP_STATUS_REG); in daqp_ai_cancel()
307 outb(0, dev->iobase + DAQP_AUX_REG); in daqp_ai_insn_read()
328 dev->iobase + DAQP_CMD_REG); in daqp_ai_insn_read()
335 inb(dev->iobase + DAQP_STATUS_REG); in daqp_ai_insn_read()
342 inb(dev->iobase + DAQP_STATUS_REG); in daqp_ai_insn_read()
474 outb(0, dev->iobase + DAQP_AUX_REG); in daqp_ai_cmd()
601 dev->iobase + DAQP_AI_FIFO_REG); in daqp_ai_cmd()
644 outb(0, dev->iobase + DAQP_AUX_REG); in daqp_ao_insn_write()
657 dev->iobase + DAQP_AO_REG); in daqp_ao_insn_write()
[all …]
A Dmultiq3.c78 dev->iobase + MULTIQ3_CTRL_REG); in multiq3_set_ctrl()
88 status = inw(dev->iobase + MULTIQ3_STATUS_REG); in multiq3_ai_status()
112 outw(0, dev->iobase + MULTIQ3_AI_CONV_REG); in multiq3_ai_insn_read()
120 val = inb(dev->iobase + MULTIQ3_AI_REG) << 8; in multiq3_ai_insn_read()
121 val |= inb(dev->iobase + MULTIQ3_AI_REG); in multiq3_ai_insn_read()
144 outw(val, dev->iobase + MULTIQ3_AO_REG); in multiq3_ao_insn_write()
156 data[1] = inw(dev->iobase + MULTIQ3_DI_REG); in multiq3_di_insn_bits()
167 outw(s->state, dev->iobase + MULTIQ3_DO_REG); in multiq3_do_insn_bits()
195 val = inb(dev->iobase + MULTIQ3_ENC_DATA_REG); in multiq3_encoder_insn_read()
196 val |= (inb(dev->iobase + MULTIQ3_ENC_DATA_REG) << 8); in multiq3_encoder_insn_read()
[all …]
A Dadv_pci1710.c342 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_ai_insn_read()
343 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_insn_read()
368 outb(0, dev->iobase + PCI171X_CLRFIFO_REG); in pci1710_ai_insn_read()
369 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_insn_read()
388 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_cancel()
414 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_handle_every_sample()
432 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_handle_every_sample()
477 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_handle_fifo()
531 outb(0, dev->iobase + PCI171X_CLRINT_REG); in pci1710_ai_cmd()
728 outw(0, dev->iobase + PCI171X_CTRL_REG); in pci1710_reset()
[all …]
/linux/drivers/rtc/
A Drtc-asm9260.c108 void __iomem *iobase; member
120 isr = ioread32(priv->iobase + HW_CIIR); in asm9260_rtc_irq()
126 iowrite32(0, priv->iobase + HW_CIIR); in asm9260_rtc_irq()
141 ctime0 = ioread32(priv->iobase + HW_CTIME0); in asm9260_rtc_read_time()
142 ctime1 = ioread32(priv->iobase + HW_CTIME1); in asm9260_rtc_read_time()
143 ctime2 = ioread32(priv->iobase + HW_CTIME2); in asm9260_rtc_read_time()
177 iowrite32(0, priv->iobase + HW_SEC); in asm9260_rtc_set_time()
263 if (IS_ERR(priv->iobase)) in asm9260_rtc_probe()
264 return PTR_ERR(priv->iobase); in asm9260_rtc_probe()
276 ccr = ioread32(priv->iobase + HW_CCR); in asm9260_rtc_probe()
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/linux/drivers/bluetooth/
A Dbt3c_cs.c132 bt3c_address(iobase, addr); in bt3c_io_write()
133 bt3c_put(iobase, value); in bt3c_io_write()
149 bt3c_address(iobase, addr); in bt3c_read()
151 return bt3c_get(iobase); in bt3c_read()
163 bt3c_address(iobase, 0x7080); in bt3c_write()
218 unsigned int iobase; in bt3c_receive() local
250 inb(iobase + DATA_H); in bt3c_receive()
286 inb(iobase + DATA_H); in bt3c_receive()
337 unsigned int iobase; in bt3c_interrupt() local
512 bt3c_put(iobase, tmp); in bt3c_load_firmware()
[all …]
A Dbluecard_cs.c171 outb(0x08 | 0x20, iobase + 0x30); in bluecard_activity_led_timeout()
190 outb(0x00, iobase + 0x30); in bluecard_enable_activity_led()
208 outb_p(actual, iobase + offset); in bluecard_write()
343 len = inb(iobase + offset); in bluecard_read()
368 unsigned int iobase; in bluecard_receive() local
497 unsigned int iobase; in bluecard_interrupt() local
644 outb(0x00, iobase + 0x30); in bluecard_hci_close()
714 id = inb(iobase + 0x30); in bluecard_open()
730 outb(0x80, iobase + 0x30); in bluecard_open()
736 outb(0x00, iobase + 0x30); in bluecard_open()
[all …]
/linux/drivers/irqchip/
A Dirq-sa11x0.c28 static void __iomem *iobase; variable
38 reg = readl_relaxed(iobase + ICMR); in sa1100_mask_irq()
40 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq()
47 reg = readl_relaxed(iobase + ICMR); in sa1100_unmask_irq()
49 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq()
136 icip = readl_relaxed(iobase + ICIP); in sa1100_handle_irq()
150 iobase = ioremap(io_start, SZ_64K); in sa11x0_init_irq_nodt()
151 if (WARN_ON(!iobase)) in sa11x0_init_irq_nodt()
155 writel_relaxed(0, iobase + ICMR); in sa11x0_init_irq_nodt()
158 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt()
[all …]
/linux/drivers/net/hamradio/
A Dbaycom_ser_fdx.c92 #define RBR(iobase) (iobase+0) argument
93 #define THR(iobase) (iobase+0) argument
94 #define IER(iobase) (iobase+1) argument
95 #define IIR(iobase) (iobase+2) argument
96 #define FCR(iobase) (iobase+2) argument
97 #define LCR(iobase) (iobase+3) argument
98 #define MCR(iobase) (iobase+4) argument
99 #define LSR(iobase) (iobase+5) argument
100 #define MSR(iobase) (iobase+6) argument
101 #define SCR(iobase) (iobase+7) argument
[all …]
A Dbaycom_ser_hdx.c78 #define RBR(iobase) (iobase+0) argument
79 #define THR(iobase) (iobase+0) argument
80 #define IER(iobase) (iobase+1) argument
81 #define IIR(iobase) (iobase+2) argument
82 #define FCR(iobase) (iobase+2) argument
83 #define LCR(iobase) (iobase+3) argument
84 #define MCR(iobase) (iobase+4) argument
85 #define LSR(iobase) (iobase+5) argument
86 #define MSR(iobase) (iobase+6) argument
87 #define SCR(iobase) (iobase+7) argument
[all …]
A Dyam.c149 #define RBR(iobase) (iobase+0) argument
150 #define THR(iobase) (iobase+0) argument
151 #define IER(iobase) (iobase+1) argument
152 #define IIR(iobase) (iobase+2) argument
153 #define FCR(iobase) (iobase+2) argument
154 #define LCR(iobase) (iobase+3) argument
155 #define MCR(iobase) (iobase+4) argument
156 #define LSR(iobase) (iobase+5) argument
157 #define MSR(iobase) (iobase+6) argument
158 #define SCR(iobase) (iobase+7) argument
[all …]
/linux/drivers/net/ethernet/dec/tulip/
A Dde4x5.h16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
41 #define EISA_ID iobase+0x0c80 /* EISA ID Registers */
42 #define EISA_ID0 iobase+0x0c80 /* EISA ID Register 0 */
43 #define EISA_ID1 iobase+0x0c81 /* EISA ID Register 1 */
44 #define EISA_ID2 iobase+0x0c82 /* EISA ID Register 2 */
45 #define EISA_ID3 iobase+0x0c83 /* EISA ID Register 3 */
46 #define EISA_CR iobase+0x0c84 /* EISA Control Register */
51 #define EISA_APROM iobase+0x0c90 /* Ethernet Address PROM */
58 #define PCI_CFRV iobase+0x0018 /* PCI Revision Register */
[all …]
/linux/drivers/i2c/busses/
A Di2c-xlr.c84 u32 __iomem *iobase; member
123 xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, in xlr_i2c_tx_irq()
133 xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN); in xlr_i2c_rx_irq()
177 xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset); in xlr_i2c_tx()
179 xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, in xlr_i2c_tx()
241 xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, in xlr_i2c_rx()
266 xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN); in xlr_i2c_rx()
318 xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0); in xlr_i2c_xfer()
383 if (IS_ERR(priv->iobase)) in xlr_i2c_probe()
384 return PTR_ERR(priv->iobase); in xlr_i2c_probe()
[all …]
A Di2c-hisi.c90 void __iomem *iobase; member
158 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
161 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
163 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
165 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
167 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
380 writel(scl_hcnt, ctlr->iobase + reg_hcnt); in hisi_i2c_set_scl()
381 writel(scl_lcnt, ctlr->iobase + reg_lcnt); in hisi_i2c_set_scl()
418 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); in hisi_i2c_configure_bus()
441 if (IS_ERR(ctlr->iobase)) in hisi_i2c_probe()
[all …]
/linux/drivers/char/pcmcia/
A Dcm4000_cs.c491 xoutb(0x80, REG_FLAGS0(iobase)); in set_protocol()
506 xoutb(i, REG_BUF_ADDR(iobase)); in set_protocol()
521 xoutb(0x50, REG_FLAGS0(iobase));
566 xoutb(0x80, REG_FLAGS0(iobase));
571 xoutb(i, REG_BUF_ADDR(iobase));
584 xoutb(0x20, REG_FLAGS1(iobase));
765 xoutb(0x80, REG_FLAGS0(iobase)); in monitor_card()
806 xoutb(i, REG_BUF_ADDR(iobase)); in monitor_card()
1153 inb(REG_FLAGS1(iobase)); in cmm_write()
1182 REG_BUF_DATA(iobase)); in cmm_write()
[all …]
/linux/drivers/char/tpm/
A Dtpm_tis_synquacer.c29 void __iomem *iobase; member
43 *result++ = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
54 iowrite8(*value++, phy->iobase + addr); in tpm_tis_synquacer_write_bytes()
69 (ioread8(phy->iobase + addr)); in tpm_tis_synquacer_read16_bw()
84 (ioread8(phy->iobase + addr + 2) << 16) | in tpm_tis_synquacer_read32_bw()
85 (ioread8(phy->iobase + addr + 1) << 8) | in tpm_tis_synquacer_read32_bw()
86 (ioread8(phy->iobase + addr)); in tpm_tis_synquacer_read32_bw()
102 iowrite8(value >> 8, phy->iobase + addr + 1); in tpm_tis_synquacer_write32_bw()
103 iowrite8(value, phy->iobase + addr); in tpm_tis_synquacer_write32_bw()
126 if (IS_ERR(phy->iobase)) in tpm_tis_synquacer_init()
[all …]
/linux/drivers/net/wan/
A Dsealevel.c39 int iobase; member
160 dev->base_addr = iobase; in slvl_setup()
204 b->iobase = iobase; in slvl_init()
209 iobase |= Z8530_PORT_SLEEP; in slvl_init()
211 dev->chanA.ctrlio = iobase + 1; in slvl_init()
212 dev->chanA.dataio = iobase; in slvl_init()
213 dev->chanB.ctrlio = iobase + 3; in slvl_init()
214 dev->chanB.dataio = iobase + 2; in slvl_init()
289 release_region(iobase, 8); in slvl_init()
310 outb(0, b->iobase); in slvl_shutdown()
[all …]

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