1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Qualcomm QMP PHY controller 9 10maintainers: 11 - Vinod Koul <vkoul@kernel.org> 12 13description: 14 QMP phy controller supports physical layer functionality for a number of 15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 16 17properties: 18 compatible: 19 enum: 20 - qcom,ipq6018-qmp-pcie-phy 21 - qcom,ipq6018-qmp-usb3-phy 22 - qcom,ipq8074-qmp-pcie-phy 23 - qcom,ipq8074-qmp-usb3-phy 24 - qcom,msm8996-qmp-pcie-phy 25 - qcom,msm8996-qmp-ufs-phy 26 - qcom,msm8996-qmp-usb3-phy 27 - qcom,msm8998-qmp-pcie-phy 28 - qcom,msm8998-qmp-ufs-phy 29 - qcom,msm8998-qmp-usb3-phy 30 - qcom,qcm2290-qmp-usb3-phy 31 - qcom,sc7180-qmp-usb3-phy 32 - qcom,sc8180x-qmp-pcie-phy 33 - qcom,sc8180x-qmp-ufs-phy 34 - qcom,sc8180x-qmp-usb3-phy 35 - qcom,sdm845-qhp-pcie-phy 36 - qcom,sdm845-qmp-pcie-phy 37 - qcom,sdm845-qmp-ufs-phy 38 - qcom,sdm845-qmp-usb3-phy 39 - qcom,sdm845-qmp-usb3-uni-phy 40 - qcom,sm6115-qmp-ufs-phy 41 - qcom,sm8150-qmp-ufs-phy 42 - qcom,sm8150-qmp-usb3-phy 43 - qcom,sm8150-qmp-usb3-uni-phy 44 - qcom,sm8250-qmp-ufs-phy 45 - qcom,sm8250-qmp-gen3x1-pcie-phy 46 - qcom,sm8250-qmp-gen3x2-pcie-phy 47 - qcom,sm8250-qmp-modem-pcie-phy 48 - qcom,sm8250-qmp-usb3-phy 49 - qcom,sm8250-qmp-usb3-uni-phy 50 - qcom,sm8350-qmp-ufs-phy 51 - qcom,sm8350-qmp-usb3-phy 52 - qcom,sm8350-qmp-usb3-uni-phy 53 - qcom,sdx55-qmp-pcie-phy 54 - qcom,sdx55-qmp-usb3-uni-phy 55 56 reg: 57 minItems: 1 58 items: 59 - description: Address and length of PHY's common serdes block. 60 - description: Address and length of PHY's DP_COM control block. 61 62 "#clock-cells": 63 enum: [ 1, 2 ] 64 65 "#address-cells": 66 enum: [ 1, 2 ] 67 68 "#size-cells": 69 enum: [ 1, 2 ] 70 71 ranges: true 72 73 clocks: 74 minItems: 1 75 maxItems: 4 76 77 clock-names: 78 minItems: 1 79 maxItems: 4 80 81 resets: 82 minItems: 1 83 maxItems: 3 84 85 reset-names: 86 minItems: 1 87 maxItems: 3 88 89 vdda-phy-supply: 90 description: 91 Phandle to a regulator supply to PHY core block. 92 93 vdda-pll-supply: 94 description: 95 Phandle to 1.8V regulator supply to PHY refclk pll block. 96 97 vddp-ref-clk-supply: 98 description: 99 Phandle to a regulator supply to any specific refclk pll block. 100 101#Required nodes: 102patternProperties: 103 "^phy@[0-9a-f]+$": 104 type: object 105 description: 106 Each device node of QMP phy is required to have as many child nodes as 107 the number of lanes the PHY has. 108 109required: 110 - compatible 111 - reg 112 - "#clock-cells" 113 - "#address-cells" 114 - "#size-cells" 115 - ranges 116 - clocks 117 - clock-names 118 - resets 119 - reset-names 120 121additionalProperties: false 122 123allOf: 124 - if: 125 properties: 126 compatible: 127 contains: 128 enum: 129 - qcom,sdm845-qmp-usb3-uni-phy 130 then: 131 properties: 132 clocks: 133 items: 134 - description: Phy aux clock. 135 - description: Phy config clock. 136 - description: 19.2 MHz ref clk. 137 - description: Phy common block aux clock. 138 clock-names: 139 items: 140 - const: aux 141 - const: cfg_ahb 142 - const: ref 143 - const: com_aux 144 resets: 145 items: 146 - description: reset of phy block. 147 - description: phy common block reset. 148 reset-names: 149 items: 150 - const: phy 151 - const: common 152 required: 153 - vdda-phy-supply 154 - vdda-pll-supply 155 - if: 156 properties: 157 compatible: 158 contains: 159 enum: 160 - qcom,sdx55-qmp-usb3-uni-phy 161 then: 162 properties: 163 clocks: 164 items: 165 - description: Phy aux clock. 166 - description: Phy config clock. 167 - description: 19.2 MHz ref clk. 168 clock-names: 169 items: 170 - const: aux 171 - const: cfg_ahb 172 - const: ref 173 resets: 174 items: 175 - description: reset of phy block. 176 - description: phy common block reset. 177 reset-names: 178 items: 179 - const: phy 180 - const: common 181 required: 182 - vdda-phy-supply 183 - vdda-pll-supply 184 - if: 185 properties: 186 compatible: 187 contains: 188 enum: 189 - qcom,msm8996-qmp-pcie-phy 190 then: 191 properties: 192 clocks: 193 items: 194 - description: Phy aux clock. 195 - description: Phy config clock. 196 - description: 19.2 MHz ref clk. 197 clock-names: 198 items: 199 - const: aux 200 - const: cfg_ahb 201 - const: ref 202 resets: 203 items: 204 - description: reset of phy block. 205 - description: phy common block reset. 206 - description: phy's ahb cfg block reset. 207 reset-names: 208 items: 209 - const: phy 210 - const: common 211 - const: cfg 212 required: 213 - vdda-phy-supply 214 - vdda-pll-supply 215 - if: 216 properties: 217 compatible: 218 contains: 219 enum: 220 - qcom,ipq8074-qmp-usb3-phy 221 - qcom,msm8996-qmp-usb3-phy 222 - qcom,msm8998-qmp-pcie-phy 223 - qcom,msm8998-qmp-usb3-phy 224 then: 225 properties: 226 clocks: 227 items: 228 - description: Phy aux clock. 229 - description: Phy config clock. 230 - description: 19.2 MHz ref clk. 231 clock-names: 232 items: 233 - const: aux 234 - const: cfg_ahb 235 - const: ref 236 resets: 237 items: 238 - description: reset of phy block. 239 - description: phy common block reset. 240 reset-names: 241 items: 242 - const: phy 243 - const: common 244 required: 245 - vdda-phy-supply 246 - vdda-pll-supply 247 - if: 248 properties: 249 compatible: 250 contains: 251 enum: 252 - qcom,msm8996-qmp-ufs-phy 253 then: 254 properties: 255 clocks: 256 items: 257 - description: 19.2 MHz ref clk. 258 clock-names: 259 items: 260 - const: ref 261 resets: 262 items: 263 - description: PHY reset in the UFS controller. 264 reset-names: 265 items: 266 - const: ufsphy 267 required: 268 - vdda-phy-supply 269 - vdda-pll-supply 270 - if: 271 properties: 272 compatible: 273 contains: 274 enum: 275 - qcom,msm8998-qmp-ufs-phy 276 - qcom,sdm845-qmp-ufs-phy 277 - qcom,sm8150-qmp-ufs-phy 278 - qcom,sm8250-qmp-ufs-phy 279 then: 280 properties: 281 clocks: 282 items: 283 - description: 19.2 MHz ref clk. 284 - description: Phy reference aux clock. 285 clock-names: 286 items: 287 - const: ref 288 - const: ref_aux 289 resets: 290 items: 291 - description: PHY reset in the UFS controller. 292 reset-names: 293 items: 294 - const: ufsphy 295 required: 296 - vdda-phy-supply 297 - vdda-pll-supply 298 - if: 299 properties: 300 compatible: 301 contains: 302 enum: 303 - qcom,ipq6018-qmp-pcie-phy 304 - qcom,ipq8074-qmp-pcie-phy 305 then: 306 properties: 307 clocks: 308 items: 309 - description: Phy aux clock. 310 - description: Phy config clock. 311 clock-names: 312 items: 313 - const: aux 314 - const: cfg_ahb 315 resets: 316 items: 317 - description: reset of phy block. 318 - description: phy common block reset. 319 reset-names: 320 items: 321 - const: phy 322 - const: common 323 - if: 324 properties: 325 compatible: 326 contains: 327 enum: 328 - qcom,sc8180x-qmp-pcie-phy 329 - qcom,sdm845-qhp-pcie-phy 330 - qcom,sdm845-qmp-pcie-phy 331 - qcom,sdx55-qmp-pcie-phy 332 - qcom,sm8250-qmp-gen3x1-pcie-phy 333 - qcom,sm8250-qmp-gen3x2-pcie-phy 334 - qcom,sm8250-qmp-modem-pcie-phy 335 then: 336 properties: 337 clocks: 338 items: 339 - description: Phy aux clock. 340 - description: Phy config clock. 341 - description: 19.2 MHz ref clk. 342 - description: Phy refgen clk. 343 clock-names: 344 items: 345 - const: aux 346 - const: cfg_ahb 347 - const: ref 348 - const: refgen 349 resets: 350 items: 351 - description: reset of phy block. 352 reset-names: 353 items: 354 - const: phy 355 required: 356 - vdda-phy-supply 357 - vdda-pll-supply 358 - if: 359 properties: 360 compatible: 361 contains: 362 enum: 363 - qcom,sm8150-qmp-usb3-phy 364 - qcom,sm8150-qmp-usb3-uni-phy 365 - qcom,sm8250-qmp-usb3-uni-phy 366 - qcom,sm8350-qmp-usb3-uni-phy 367 then: 368 properties: 369 clocks: 370 items: 371 - description: Phy aux clock. 372 - description: 19.2 MHz ref clk source. 373 - description: 19.2 MHz ref clk. 374 - description: Phy common block aux clock. 375 clock-names: 376 items: 377 - const: aux 378 - const: ref_clk_src 379 - const: ref 380 - const: com_aux 381 resets: 382 items: 383 - description: reset of phy block. 384 - description: phy common block reset. 385 reset-names: 386 items: 387 - const: phy 388 - const: common 389 required: 390 - vdda-phy-supply 391 - vdda-pll-supply 392 - if: 393 properties: 394 compatible: 395 contains: 396 enum: 397 - qcom,sm8250-qmp-usb3-phy 398 - qcom,sm8350-qmp-usb3-phy 399 then: 400 properties: 401 clocks: 402 items: 403 - description: Phy aux clock. 404 - description: 19.2 MHz ref clk. 405 - description: Phy common block aux clock. 406 clock-names: 407 items: 408 - const: aux 409 - const: ref_clk_src 410 - const: com_aux 411 resets: 412 items: 413 - description: reset of phy block. 414 - description: phy common block reset. 415 reset-names: 416 items: 417 - const: phy 418 - const: common 419 required: 420 - vdda-phy-supply 421 - vdda-pll-supply 422 - if: 423 properties: 424 compatible: 425 contains: 426 enum: 427 - qcom,qcm2290-qmp-usb3-phy 428 then: 429 properties: 430 clocks: 431 items: 432 - description: Phy config clock. 433 - description: 19.2 MHz ref clk. 434 - description: Phy common block aux clock. 435 clock-names: 436 items: 437 - const: cfg_ahb 438 - const: ref 439 - const: com_aux 440 resets: 441 items: 442 - description: phy_phy reset. 443 - description: reset of phy block. 444 reset-names: 445 items: 446 - const: phy_phy 447 - const: phy 448 required: 449 - vdda-phy-supply 450 - vdda-pll-supply 451 452examples: 453 - | 454 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 455 usb_2_qmpphy: phy-wrapper@88eb000 { 456 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 457 reg = <0x088eb000 0x18c>; 458 #clock-cells = <1>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 ranges = <0x0 0x088eb000 0x2000>; 462 463 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, 464 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 465 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 466 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 467 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 468 469 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 470 <&gcc GCC_USB3_PHY_SEC_BCR>; 471 reset-names = "phy", "common"; 472 473 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 474 vdda-pll-supply = <&vdda_usb2_ss_core>; 475 476 usb_2_ssphy: phy@200 { 477 reg = <0x200 0x128>, 478 <0x400 0x1fc>, 479 <0x800 0x218>, 480 <0x600 0x70>; 481 #clock-cells = <0>; 482 #phy-cells = <0>; 483 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 484 clock-names = "pipe0"; 485 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 486 }; 487 }; 488