1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
61 */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
73 #include <linux/mm.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <asm/cpu.h>
77 #include <asm/cpufeature.h>
78 #include <asm/cpu_ops.h>
79 #include <asm/fpsimd.h>
80 #include <asm/insn.h>
81 #include <asm/kvm_host.h>
82 #include <asm/mmu_context.h>
83 #include <asm/mte.h>
84 #include <asm/processor.h>
85 #include <asm/smp.h>
86 #include <asm/sysreg.h>
87 #include <asm/traps.h>
88 #include <asm/virt.h>
89
90 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
91 static unsigned long elf_hwcap __read_mostly;
92
93 #ifdef CONFIG_COMPAT
94 #define COMPAT_ELF_HWCAP_DEFAULT \
95 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
96 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
97 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
98 COMPAT_HWCAP_LPAE)
99 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
100 unsigned int compat_elf_hwcap2 __read_mostly;
101 #endif
102
103 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
104 EXPORT_SYMBOL(cpu_hwcaps);
105 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
106
107 /* Need also bit for ARM64_CB_PATCH */
108 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
109
110 bool arm64_use_ng_mappings = false;
111 EXPORT_SYMBOL(arm64_use_ng_mappings);
112
113 /*
114 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
115 * support it?
116 */
117 static bool __read_mostly allow_mismatched_32bit_el0;
118
119 /*
120 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
121 * seen at least one CPU capable of 32-bit EL0.
122 */
123 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
124
125 /*
126 * Mask of CPUs supporting 32-bit EL0.
127 * Only valid if arm64_mismatched_32bit_el0 is enabled.
128 */
129 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
130
131 /*
132 * Flag to indicate if we have computed the system wide
133 * capabilities based on the boot time active CPUs. This
134 * will be used to determine if a new booting CPU should
135 * go through the verification process to make sure that it
136 * supports the system capabilities, without using a hotplug
137 * notifier. This is also used to decide if we could use
138 * the fast path for checking constant CPU caps.
139 */
140 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
141 EXPORT_SYMBOL(arm64_const_caps_ready);
finalize_system_capabilities(void)142 static inline void finalize_system_capabilities(void)
143 {
144 static_branch_enable(&arm64_const_caps_ready);
145 }
146
dump_cpu_features(void)147 void dump_cpu_features(void)
148 {
149 /* file-wide pr_fmt adds "CPU features: " prefix */
150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
151 }
152
153 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
154 EXPORT_SYMBOL(cpu_hwcap_keys);
155
156 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157 { \
158 .sign = SIGNED, \
159 .visible = VISIBLE, \
160 .strict = STRICT, \
161 .type = TYPE, \
162 .shift = SHIFT, \
163 .width = WIDTH, \
164 .safe_val = SAFE_VAL, \
165 }
166
167 /* Define a feature with unsigned values */
168 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
169 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
170
171 /* Define a feature with a signed value */
172 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
173 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
174
175 #define ARM64_FTR_END \
176 { \
177 .width = 0, \
178 }
179
180 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
181
182 static bool __system_matches_cap(unsigned int n);
183
184 /*
185 * NOTE: Any changes to the visibility of features should be kept in
186 * sync with the documentation of the CPU feature register ABI.
187 */
188 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
203 ARM64_FTR_END,
204 };
205
206 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
216 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
221 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
223 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
225 ARM64_FTR_END,
226 };
227
228 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
236 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
239 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
240 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
245 ARM64_FTR_END,
246 };
247
248 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
256 ARM64_FTR_END,
257 };
258
259 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
278 ARM64_FTR_END,
279 };
280
281 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
282 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
285 /*
286 * Page size not being supported at Stage-2 is not fatal. You
287 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
288 * your favourite nesting hypervisor.
289 *
290 * There is a small corner case where the hypervisor explicitly
291 * advertises a given granule size at Stage-2 (value 2) on some
292 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
293 * vCPUs. Although this is not forbidden by the architecture, it
294 * indicates that the hypervisor is being silly (or buggy).
295 *
296 * We make no effort to cope with this and pretend that if these
297 * fields are inconsistent across vCPUs, then it isn't worth
298 * trying to bring KVM up.
299 */
300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
303 /*
304 * We already refuse to boot CPUs that don't support our configured
305 * page size, so we can only detect mismatches for a page size other
306 * than the one we're currently using. Unfortunately, SoCs like this
307 * exist in the wild so, even though we don't like it, we'll have to go
308 * along with it and treat them as non-strict.
309 */
310 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
311 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
313
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
315 /* Linux shouldn't care about secure memory */
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
319 /*
320 * Differing PARange is fine as long as all peripherals and memory are mapped
321 * within the minimum PARange of all CPUs
322 */
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
324 ARM64_FTR_END,
325 };
326
327 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
338 ARM64_FTR_END,
339 };
340
341 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
357 ARM64_FTR_END,
358 };
359
360 static const struct arm64_ftr_bits ftr_ctr[] = {
361 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
362 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
367 /*
368 * Linux can handle differing I-cache policies. Userspace JITs will
369 * make use of *minLine.
370 * If we have differing I-cache policies, report it as the weakest - VIPT.
371 */
372 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
373 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
374 ARM64_FTR_END,
375 };
376
377 static struct arm64_ftr_override __ro_after_init no_override = { };
378
379 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
380 .name = "SYS_CTR_EL0",
381 .ftr_bits = ftr_ctr,
382 .override = &no_override,
383 };
384
385 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
386 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
391 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
394 ARM64_FTR_END,
395 };
396
397 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
398 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
403 /*
404 * We can instantiate multiple PMU instances with different levels
405 * of support.
406 */
407 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
409 ARM64_FTR_END,
410 };
411
412 static const struct arm64_ftr_bits ftr_mvfr2[] = {
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
415 ARM64_FTR_END,
416 };
417
418 static const struct arm64_ftr_bits ftr_dczid[] = {
419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
421 ARM64_FTR_END,
422 };
423
424 static const struct arm64_ftr_bits ftr_gmid[] = {
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
426 ARM64_FTR_END,
427 };
428
429 static const struct arm64_ftr_bits ftr_id_isar0[] = {
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
437 ARM64_FTR_END,
438 };
439
440 static const struct arm64_ftr_bits ftr_id_isar5[] = {
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
447 ARM64_FTR_END,
448 };
449
450 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
458
459 /*
460 * SpecSEI = 1 indicates that the PE might generate an SError on an
461 * external abort on speculative read. It is safe to assume that an
462 * SError might be generated than it will not be. Hence it has been
463 * classified as FTR_HIGHER_SAFE.
464 */
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
466 ARM64_FTR_END,
467 };
468
469 static const struct arm64_ftr_bits ftr_id_isar4[] = {
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
478 ARM64_FTR_END,
479 };
480
481 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
483 ARM64_FTR_END,
484 };
485
486 static const struct arm64_ftr_bits ftr_id_isar6[] = {
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
494 ARM64_FTR_END,
495 };
496
497 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
504 ARM64_FTR_END,
505 };
506
507 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
516 ARM64_FTR_END,
517 };
518
519 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
522 ARM64_FTR_END,
523 };
524
525 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
526 /* [31:28] TraceFilt */
527 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
534 ARM64_FTR_END,
535 };
536
537 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
538 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
539 ARM64_FTR_END,
540 };
541
542 static const struct arm64_ftr_bits ftr_zcr[] = {
543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
544 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
545 ARM64_FTR_END,
546 };
547
548 /*
549 * Common ftr bits for a 32bit register with all hidden, strict
550 * attributes, with 4bit feature fields and a default safe value of
551 * 0. Covers the following 32bit registers:
552 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
553 */
554 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
563 ARM64_FTR_END,
564 };
565
566 /* Table for a single 32bit feature value */
567 static const struct arm64_ftr_bits ftr_single32[] = {
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
569 ARM64_FTR_END,
570 };
571
572 static const struct arm64_ftr_bits ftr_raz[] = {
573 ARM64_FTR_END,
574 };
575
576 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
577 .sys_id = id, \
578 .reg = &(struct arm64_ftr_reg){ \
579 .name = id_str, \
580 .override = (ovr), \
581 .ftr_bits = &((table)[0]), \
582 }}
583
584 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
585 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
586
587 #define ARM64_FTR_REG(id, table) \
588 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
589
590 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
591 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
592 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
593
594 static const struct __ftr_reg_entry {
595 u32 sys_id;
596 struct arm64_ftr_reg *reg;
597 } arm64_ftr_regs[] = {
598
599 /* Op1 = 0, CRn = 0, CRm = 1 */
600 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
601 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
602 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
603 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
604 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
605 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
606 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
607
608 /* Op1 = 0, CRn = 0, CRm = 2 */
609 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
610 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
611 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
612 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
613 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
614 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
615 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
616 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
617
618 /* Op1 = 0, CRn = 0, CRm = 3 */
619 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
620 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
621 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
622 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
623 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
624 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
625
626 /* Op1 = 0, CRn = 0, CRm = 4 */
627 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
628 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
629 &id_aa64pfr1_override),
630 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
631
632 /* Op1 = 0, CRn = 0, CRm = 5 */
633 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
634 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
635
636 /* Op1 = 0, CRn = 0, CRm = 6 */
637 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
638 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
639 &id_aa64isar1_override),
640
641 /* Op1 = 0, CRn = 0, CRm = 7 */
642 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
643 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
644 &id_aa64mmfr1_override),
645 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
646
647 /* Op1 = 0, CRn = 1, CRm = 2 */
648 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
649
650 /* Op1 = 1, CRn = 0, CRm = 0 */
651 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
652
653 /* Op1 = 3, CRn = 0, CRm = 0 */
654 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
655 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
656
657 /* Op1 = 3, CRn = 14, CRm = 0 */
658 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
659 };
660
search_cmp_ftr_reg(const void * id,const void * regp)661 static int search_cmp_ftr_reg(const void *id, const void *regp)
662 {
663 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
664 }
665
666 /*
667 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
668 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
669 * ascending order of sys_id, we use binary search to find a matching
670 * entry.
671 *
672 * returns - Upon success, matching ftr_reg entry for id.
673 * - NULL on failure. It is upto the caller to decide
674 * the impact of a failure.
675 */
get_arm64_ftr_reg_nowarn(u32 sys_id)676 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
677 {
678 const struct __ftr_reg_entry *ret;
679
680 ret = bsearch((const void *)(unsigned long)sys_id,
681 arm64_ftr_regs,
682 ARRAY_SIZE(arm64_ftr_regs),
683 sizeof(arm64_ftr_regs[0]),
684 search_cmp_ftr_reg);
685 if (ret)
686 return ret->reg;
687 return NULL;
688 }
689
690 /*
691 * get_arm64_ftr_reg - Looks up a feature register entry using
692 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
693 *
694 * returns - Upon success, matching ftr_reg entry for id.
695 * - NULL on failure but with an WARN_ON().
696 */
get_arm64_ftr_reg(u32 sys_id)697 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
698 {
699 struct arm64_ftr_reg *reg;
700
701 reg = get_arm64_ftr_reg_nowarn(sys_id);
702
703 /*
704 * Requesting a non-existent register search is an error. Warn
705 * and let the caller handle it.
706 */
707 WARN_ON(!reg);
708 return reg;
709 }
710
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)711 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
712 s64 ftr_val)
713 {
714 u64 mask = arm64_ftr_mask(ftrp);
715
716 reg &= ~mask;
717 reg |= (ftr_val << ftrp->shift) & mask;
718 return reg;
719 }
720
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)721 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
722 s64 cur)
723 {
724 s64 ret = 0;
725
726 switch (ftrp->type) {
727 case FTR_EXACT:
728 ret = ftrp->safe_val;
729 break;
730 case FTR_LOWER_SAFE:
731 ret = min(new, cur);
732 break;
733 case FTR_HIGHER_OR_ZERO_SAFE:
734 if (!cur || !new)
735 break;
736 fallthrough;
737 case FTR_HIGHER_SAFE:
738 ret = max(new, cur);
739 break;
740 default:
741 BUG();
742 }
743
744 return ret;
745 }
746
sort_ftr_regs(void)747 static void __init sort_ftr_regs(void)
748 {
749 unsigned int i;
750
751 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
752 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
753 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
754 unsigned int j = 0;
755
756 /*
757 * Features here must be sorted in descending order with respect
758 * to their shift values and should not overlap with each other.
759 */
760 for (; ftr_bits->width != 0; ftr_bits++, j++) {
761 unsigned int width = ftr_reg->ftr_bits[j].width;
762 unsigned int shift = ftr_reg->ftr_bits[j].shift;
763 unsigned int prev_shift;
764
765 WARN((shift + width) > 64,
766 "%s has invalid feature at shift %d\n",
767 ftr_reg->name, shift);
768
769 /*
770 * Skip the first feature. There is nothing to
771 * compare against for now.
772 */
773 if (j == 0)
774 continue;
775
776 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
777 WARN((shift + width) > prev_shift,
778 "%s has feature overlap at shift %d\n",
779 ftr_reg->name, shift);
780 }
781
782 /*
783 * Skip the first register. There is nothing to
784 * compare against for now.
785 */
786 if (i == 0)
787 continue;
788 /*
789 * Registers here must be sorted in ascending order with respect
790 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
791 * to work correctly.
792 */
793 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
794 }
795 }
796
797 /*
798 * Initialise the CPU feature register from Boot CPU values.
799 * Also initiliases the strict_mask for the register.
800 * Any bits that are not covered by an arm64_ftr_bits entry are considered
801 * RES0 for the system-wide value, and must strictly match.
802 */
init_cpu_ftr_reg(u32 sys_reg,u64 new)803 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
804 {
805 u64 val = 0;
806 u64 strict_mask = ~0x0ULL;
807 u64 user_mask = 0;
808 u64 valid_mask = 0;
809
810 const struct arm64_ftr_bits *ftrp;
811 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
812
813 if (!reg)
814 return;
815
816 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
817 u64 ftr_mask = arm64_ftr_mask(ftrp);
818 s64 ftr_new = arm64_ftr_value(ftrp, new);
819 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
820
821 if ((ftr_mask & reg->override->mask) == ftr_mask) {
822 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
823 char *str = NULL;
824
825 if (ftr_ovr != tmp) {
826 /* Unsafe, remove the override */
827 reg->override->mask &= ~ftr_mask;
828 reg->override->val &= ~ftr_mask;
829 tmp = ftr_ovr;
830 str = "ignoring override";
831 } else if (ftr_new != tmp) {
832 /* Override was valid */
833 ftr_new = tmp;
834 str = "forced";
835 } else if (ftr_ovr == tmp) {
836 /* Override was the safe value */
837 str = "already set";
838 }
839
840 if (str)
841 pr_warn("%s[%d:%d]: %s to %llx\n",
842 reg->name,
843 ftrp->shift + ftrp->width - 1,
844 ftrp->shift, str, tmp);
845 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
846 reg->override->val &= ~ftr_mask;
847 pr_warn("%s[%d:%d]: impossible override, ignored\n",
848 reg->name,
849 ftrp->shift + ftrp->width - 1,
850 ftrp->shift);
851 }
852
853 val = arm64_ftr_set_value(ftrp, val, ftr_new);
854
855 valid_mask |= ftr_mask;
856 if (!ftrp->strict)
857 strict_mask &= ~ftr_mask;
858 if (ftrp->visible)
859 user_mask |= ftr_mask;
860 else
861 reg->user_val = arm64_ftr_set_value(ftrp,
862 reg->user_val,
863 ftrp->safe_val);
864 }
865
866 val &= valid_mask;
867
868 reg->sys_val = val;
869 reg->strict_mask = strict_mask;
870 reg->user_mask = user_mask;
871 }
872
873 extern const struct arm64_cpu_capabilities arm64_errata[];
874 static const struct arm64_cpu_capabilities arm64_features[];
875
876 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)877 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
878 {
879 for (; caps->matches; caps++) {
880 if (WARN(caps->capability >= ARM64_NCAPS,
881 "Invalid capability %d\n", caps->capability))
882 continue;
883 if (WARN(cpu_hwcaps_ptrs[caps->capability],
884 "Duplicate entry for capability %d\n",
885 caps->capability))
886 continue;
887 cpu_hwcaps_ptrs[caps->capability] = caps;
888 }
889 }
890
init_cpu_hwcaps_indirect_list(void)891 static void __init init_cpu_hwcaps_indirect_list(void)
892 {
893 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
894 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
895 }
896
897 static void __init setup_boot_cpu_capabilities(void);
898
init_32bit_cpu_features(struct cpuinfo_32bit * info)899 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
900 {
901 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
902 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
903 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
904 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
905 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
906 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
907 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
908 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
909 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
910 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
911 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
912 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
913 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
914 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
915 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
916 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
917 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
918 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
919 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
920 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
921 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
922 }
923
init_cpu_features(struct cpuinfo_arm64 * info)924 void __init init_cpu_features(struct cpuinfo_arm64 *info)
925 {
926 /* Before we start using the tables, make sure it is sorted */
927 sort_ftr_regs();
928
929 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
930 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
931 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
932 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
933 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
934 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
935 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
936 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
937 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
938 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
939 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
940 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
941 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
942
943 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
944 init_32bit_cpu_features(&info->aarch32);
945
946 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
947 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
948 vec_init_vq_map(ARM64_VEC_SVE);
949 }
950
951 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
952 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
953
954 /*
955 * Initialize the indirect array of CPU hwcaps capabilities pointers
956 * before we handle the boot CPU below.
957 */
958 init_cpu_hwcaps_indirect_list();
959
960 /*
961 * Detect and enable early CPU capabilities based on the boot CPU,
962 * after we have initialised the CPU feature infrastructure.
963 */
964 setup_boot_cpu_capabilities();
965 }
966
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)967 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
968 {
969 const struct arm64_ftr_bits *ftrp;
970
971 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
972 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
973 s64 ftr_new = arm64_ftr_value(ftrp, new);
974
975 if (ftr_cur == ftr_new)
976 continue;
977 /* Find a safe value */
978 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
979 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
980 }
981
982 }
983
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)984 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
985 {
986 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
987
988 if (!regp)
989 return 0;
990
991 update_cpu_ftr_reg(regp, val);
992 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
993 return 0;
994 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
995 regp->name, boot, cpu, val);
996 return 1;
997 }
998
relax_cpu_ftr_reg(u32 sys_id,int field)999 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1000 {
1001 const struct arm64_ftr_bits *ftrp;
1002 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1003
1004 if (!regp)
1005 return;
1006
1007 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1008 if (ftrp->shift == field) {
1009 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1010 break;
1011 }
1012 }
1013
1014 /* Bogus field? */
1015 WARN_ON(!ftrp->width);
1016 }
1017
lazy_init_32bit_cpu_features(struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1018 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1019 struct cpuinfo_arm64 *boot)
1020 {
1021 static bool boot_cpu_32bit_regs_overridden = false;
1022
1023 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1024 return;
1025
1026 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1027 return;
1028
1029 boot->aarch32 = info->aarch32;
1030 init_32bit_cpu_features(&boot->aarch32);
1031 boot_cpu_32bit_regs_overridden = true;
1032 }
1033
update_32bit_cpu_features(int cpu,struct cpuinfo_32bit * info,struct cpuinfo_32bit * boot)1034 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1035 struct cpuinfo_32bit *boot)
1036 {
1037 int taint = 0;
1038 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1039
1040 /*
1041 * If we don't have AArch32 at EL1, then relax the strictness of
1042 * EL1-dependent register fields to avoid spurious sanity check fails.
1043 */
1044 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1045 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1046 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1047 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1048 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1049 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1050 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1051 }
1052
1053 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1054 info->reg_id_dfr0, boot->reg_id_dfr0);
1055 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1056 info->reg_id_dfr1, boot->reg_id_dfr1);
1057 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1058 info->reg_id_isar0, boot->reg_id_isar0);
1059 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1060 info->reg_id_isar1, boot->reg_id_isar1);
1061 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1062 info->reg_id_isar2, boot->reg_id_isar2);
1063 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1064 info->reg_id_isar3, boot->reg_id_isar3);
1065 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1066 info->reg_id_isar4, boot->reg_id_isar4);
1067 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1068 info->reg_id_isar5, boot->reg_id_isar5);
1069 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1070 info->reg_id_isar6, boot->reg_id_isar6);
1071
1072 /*
1073 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1074 * ACTLR formats could differ across CPUs and therefore would have to
1075 * be trapped for virtualization anyway.
1076 */
1077 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1078 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1079 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1080 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1081 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1082 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1083 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1084 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1085 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1086 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1087 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1088 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1089 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1090 info->reg_id_pfr0, boot->reg_id_pfr0);
1091 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1092 info->reg_id_pfr1, boot->reg_id_pfr1);
1093 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1094 info->reg_id_pfr2, boot->reg_id_pfr2);
1095 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1096 info->reg_mvfr0, boot->reg_mvfr0);
1097 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1098 info->reg_mvfr1, boot->reg_mvfr1);
1099 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1100 info->reg_mvfr2, boot->reg_mvfr2);
1101
1102 return taint;
1103 }
1104
1105 /*
1106 * Update system wide CPU feature registers with the values from a
1107 * non-boot CPU. Also performs SANITY checks to make sure that there
1108 * aren't any insane variations from that of the boot CPU.
1109 */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1110 void update_cpu_features(int cpu,
1111 struct cpuinfo_arm64 *info,
1112 struct cpuinfo_arm64 *boot)
1113 {
1114 int taint = 0;
1115
1116 /*
1117 * The kernel can handle differing I-cache policies, but otherwise
1118 * caches should look identical. Userspace JITs will make use of
1119 * *minLine.
1120 */
1121 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1122 info->reg_ctr, boot->reg_ctr);
1123
1124 /*
1125 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1126 * could result in too much or too little memory being zeroed if a
1127 * process is preempted and migrated between CPUs.
1128 */
1129 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1130 info->reg_dczid, boot->reg_dczid);
1131
1132 /* If different, timekeeping will be broken (especially with KVM) */
1133 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1134 info->reg_cntfrq, boot->reg_cntfrq);
1135
1136 /*
1137 * The kernel uses self-hosted debug features and expects CPUs to
1138 * support identical debug features. We presently need CTX_CMPs, WRPs,
1139 * and BRPs to be identical.
1140 * ID_AA64DFR1 is currently RES0.
1141 */
1142 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1143 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1144 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1145 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1146 /*
1147 * Even in big.LITTLE, processors should be identical instruction-set
1148 * wise.
1149 */
1150 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1151 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1152 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1153 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1154
1155 /*
1156 * Differing PARange support is fine as long as all peripherals and
1157 * memory are mapped within the minimum PARange of all CPUs.
1158 * Linux should not care about secure memory.
1159 */
1160 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1161 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1162 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1163 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1164 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1165 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1166
1167 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1168 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1169 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1170 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1171
1172 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1173 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1174
1175 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1176 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1177 info->reg_zcr, boot->reg_zcr);
1178
1179 /* Probe vector lengths, unless we already gave up on SVE */
1180 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1181 !system_capabilities_finalized())
1182 vec_update_vq_map(ARM64_VEC_SVE);
1183 }
1184
1185 /*
1186 * The kernel uses the LDGM/STGM instructions and the number of tags
1187 * they read/write depends on the GMID_EL1.BS field. Check that the
1188 * value is the same on all CPUs.
1189 */
1190 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1191 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1192 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1193 info->reg_gmid, boot->reg_gmid);
1194 }
1195
1196 /*
1197 * If we don't have AArch32 at all then skip the checks entirely
1198 * as the register values may be UNKNOWN and we're not going to be
1199 * using them for anything.
1200 *
1201 * This relies on a sanitised view of the AArch64 ID registers
1202 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1203 */
1204 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1205 lazy_init_32bit_cpu_features(info, boot);
1206 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1207 &boot->aarch32);
1208 }
1209
1210 /*
1211 * Mismatched CPU features are a recipe for disaster. Don't even
1212 * pretend to support them.
1213 */
1214 if (taint) {
1215 pr_warn_once("Unsupported CPU feature variation detected.\n");
1216 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1217 }
1218 }
1219
read_sanitised_ftr_reg(u32 id)1220 u64 read_sanitised_ftr_reg(u32 id)
1221 {
1222 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1223
1224 if (!regp)
1225 return 0;
1226 return regp->sys_val;
1227 }
1228 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1229
1230 #define read_sysreg_case(r) \
1231 case r: val = read_sysreg_s(r); break;
1232
1233 /*
1234 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1235 * Read the system register on the current CPU
1236 */
__read_sysreg_by_encoding(u32 sys_id)1237 u64 __read_sysreg_by_encoding(u32 sys_id)
1238 {
1239 struct arm64_ftr_reg *regp;
1240 u64 val;
1241
1242 switch (sys_id) {
1243 read_sysreg_case(SYS_ID_PFR0_EL1);
1244 read_sysreg_case(SYS_ID_PFR1_EL1);
1245 read_sysreg_case(SYS_ID_PFR2_EL1);
1246 read_sysreg_case(SYS_ID_DFR0_EL1);
1247 read_sysreg_case(SYS_ID_DFR1_EL1);
1248 read_sysreg_case(SYS_ID_MMFR0_EL1);
1249 read_sysreg_case(SYS_ID_MMFR1_EL1);
1250 read_sysreg_case(SYS_ID_MMFR2_EL1);
1251 read_sysreg_case(SYS_ID_MMFR3_EL1);
1252 read_sysreg_case(SYS_ID_MMFR4_EL1);
1253 read_sysreg_case(SYS_ID_MMFR5_EL1);
1254 read_sysreg_case(SYS_ID_ISAR0_EL1);
1255 read_sysreg_case(SYS_ID_ISAR1_EL1);
1256 read_sysreg_case(SYS_ID_ISAR2_EL1);
1257 read_sysreg_case(SYS_ID_ISAR3_EL1);
1258 read_sysreg_case(SYS_ID_ISAR4_EL1);
1259 read_sysreg_case(SYS_ID_ISAR5_EL1);
1260 read_sysreg_case(SYS_ID_ISAR6_EL1);
1261 read_sysreg_case(SYS_MVFR0_EL1);
1262 read_sysreg_case(SYS_MVFR1_EL1);
1263 read_sysreg_case(SYS_MVFR2_EL1);
1264
1265 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1266 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1267 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1268 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1269 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1270 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1271 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1272 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1273 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1274 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1275
1276 read_sysreg_case(SYS_CNTFRQ_EL0);
1277 read_sysreg_case(SYS_CTR_EL0);
1278 read_sysreg_case(SYS_DCZID_EL0);
1279
1280 default:
1281 BUG();
1282 return 0;
1283 }
1284
1285 regp = get_arm64_ftr_reg(sys_id);
1286 if (regp) {
1287 val &= ~regp->override->mask;
1288 val |= (regp->override->val & regp->override->mask);
1289 }
1290
1291 return val;
1292 }
1293
1294 #include <linux/irqchip/arm-gic-v3.h>
1295
1296 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)1297 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1298 {
1299 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1300
1301 return val >= entry->min_field_value;
1302 }
1303
1304 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1305 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1306 {
1307 u64 val;
1308
1309 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1310 if (scope == SCOPE_SYSTEM)
1311 val = read_sanitised_ftr_reg(entry->sys_reg);
1312 else
1313 val = __read_sysreg_by_encoding(entry->sys_reg);
1314
1315 return feature_matches(val, entry);
1316 }
1317
system_32bit_el0_cpumask(void)1318 const struct cpumask *system_32bit_el0_cpumask(void)
1319 {
1320 if (!system_supports_32bit_el0())
1321 return cpu_none_mask;
1322
1323 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1324 return cpu_32bit_el0_mask;
1325
1326 return cpu_possible_mask;
1327 }
1328
parse_32bit_el0_param(char * str)1329 static int __init parse_32bit_el0_param(char *str)
1330 {
1331 allow_mismatched_32bit_el0 = true;
1332 return 0;
1333 }
1334 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1335
aarch32_el0_show(struct device * dev,struct device_attribute * attr,char * buf)1336 static ssize_t aarch32_el0_show(struct device *dev,
1337 struct device_attribute *attr, char *buf)
1338 {
1339 const struct cpumask *mask = system_32bit_el0_cpumask();
1340
1341 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1342 }
1343 static const DEVICE_ATTR_RO(aarch32_el0);
1344
aarch32_el0_sysfs_init(void)1345 static int __init aarch32_el0_sysfs_init(void)
1346 {
1347 if (!allow_mismatched_32bit_el0)
1348 return 0;
1349
1350 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1351 }
1352 device_initcall(aarch32_el0_sysfs_init);
1353
has_32bit_el0(const struct arm64_cpu_capabilities * entry,int scope)1354 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1355 {
1356 if (!has_cpuid_feature(entry, scope))
1357 return allow_mismatched_32bit_el0;
1358
1359 if (scope == SCOPE_SYSTEM)
1360 pr_info("detected: 32-bit EL0 Support\n");
1361
1362 return true;
1363 }
1364
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)1365 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1366 {
1367 bool has_sre;
1368
1369 if (!has_cpuid_feature(entry, scope))
1370 return false;
1371
1372 has_sre = gic_enable_sre();
1373 if (!has_sre)
1374 pr_warn_once("%s present but disabled by higher exception level\n",
1375 entry->desc);
1376
1377 return has_sre;
1378 }
1379
has_no_hw_prefetch(const struct arm64_cpu_capabilities * entry,int __unused)1380 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1381 {
1382 u32 midr = read_cpuid_id();
1383
1384 /* Cavium ThunderX pass 1.x and 2.x */
1385 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1386 MIDR_CPU_VAR_REV(0, 0),
1387 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1388 }
1389
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)1390 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1391 {
1392 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1393
1394 return cpuid_feature_extract_signed_field(pfr0,
1395 ID_AA64PFR0_FP_SHIFT) < 0;
1396 }
1397
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)1398 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1399 int scope)
1400 {
1401 u64 ctr;
1402
1403 if (scope == SCOPE_SYSTEM)
1404 ctr = arm64_ftr_reg_ctrel0.sys_val;
1405 else
1406 ctr = read_cpuid_effective_cachetype();
1407
1408 return ctr & BIT(CTR_IDC_SHIFT);
1409 }
1410
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)1411 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1412 {
1413 /*
1414 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1415 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1416 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1417 * value.
1418 */
1419 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1420 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1421 }
1422
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)1423 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1424 int scope)
1425 {
1426 u64 ctr;
1427
1428 if (scope == SCOPE_SYSTEM)
1429 ctr = arm64_ftr_reg_ctrel0.sys_val;
1430 else
1431 ctr = read_cpuid_cachetype();
1432
1433 return ctr & BIT(CTR_DIC_SHIFT);
1434 }
1435
1436 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)1437 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1438 {
1439 /*
1440 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1441 * may share TLB entries with a CPU stuck in the crashed
1442 * kernel.
1443 */
1444 if (is_kdump_kernel())
1445 return false;
1446
1447 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1448 return false;
1449
1450 return has_cpuid_feature(entry, scope);
1451 }
1452
1453 /*
1454 * This check is triggered during the early boot before the cpufeature
1455 * is initialised. Checking the status on the local CPU allows the boot
1456 * CPU to detect the need for non-global mappings and thus avoiding a
1457 * pagetable re-write after all the CPUs are booted. This check will be
1458 * anyway run on individual CPUs, allowing us to get the consistent
1459 * state once the SMP CPUs are up and thus make the switch to non-global
1460 * mappings if required.
1461 */
kaslr_requires_kpti(void)1462 bool kaslr_requires_kpti(void)
1463 {
1464 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1465 return false;
1466
1467 /*
1468 * E0PD does a similar job to KPTI so can be used instead
1469 * where available.
1470 */
1471 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1472 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1473 if (cpuid_feature_extract_unsigned_field(mmfr2,
1474 ID_AA64MMFR2_E0PD_SHIFT))
1475 return false;
1476 }
1477
1478 /*
1479 * Systems affected by Cavium erratum 24756 are incompatible
1480 * with KPTI.
1481 */
1482 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1483 extern const struct midr_range cavium_erratum_27456_cpus[];
1484
1485 if (is_midr_in_range_list(read_cpuid_id(),
1486 cavium_erratum_27456_cpus))
1487 return false;
1488 }
1489
1490 return kaslr_offset() > 0;
1491 }
1492
1493 static bool __meltdown_safe = true;
1494 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1495
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)1496 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1497 int scope)
1498 {
1499 /* List of CPUs that are not vulnerable and don't need KPTI */
1500 static const struct midr_range kpti_safe_list[] = {
1501 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1502 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1503 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1504 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1505 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1506 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1507 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1508 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1509 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1510 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1511 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1512 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1513 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1514 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1515 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1516 { /* sentinel */ }
1517 };
1518 char const *str = "kpti command line option";
1519 bool meltdown_safe;
1520
1521 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1522
1523 /* Defer to CPU feature registers */
1524 if (has_cpuid_feature(entry, scope))
1525 meltdown_safe = true;
1526
1527 if (!meltdown_safe)
1528 __meltdown_safe = false;
1529
1530 /*
1531 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1532 * ThunderX leads to apparent I-cache corruption of kernel text, which
1533 * ends as well as you might imagine. Don't even try. We cannot rely
1534 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1535 * because cpucap detection order may change. However, since we know
1536 * affected CPUs are always in a homogeneous configuration, it is
1537 * safe to rely on this_cpu_has_cap() here.
1538 */
1539 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1540 str = "ARM64_WORKAROUND_CAVIUM_27456";
1541 __kpti_forced = -1;
1542 }
1543
1544 /* Useful for KASLR robustness */
1545 if (kaslr_requires_kpti()) {
1546 if (!__kpti_forced) {
1547 str = "KASLR";
1548 __kpti_forced = 1;
1549 }
1550 }
1551
1552 if (cpu_mitigations_off() && !__kpti_forced) {
1553 str = "mitigations=off";
1554 __kpti_forced = -1;
1555 }
1556
1557 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1558 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1559 return false;
1560 }
1561
1562 /* Forced? */
1563 if (__kpti_forced) {
1564 pr_info_once("kernel page table isolation forced %s by %s\n",
1565 __kpti_forced > 0 ? "ON" : "OFF", str);
1566 return __kpti_forced > 0;
1567 }
1568
1569 return !meltdown_safe;
1570 }
1571
1572 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1573 static void __nocfi
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1574 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1575 {
1576 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1577 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1578 kpti_remap_fn *remap_fn;
1579
1580 int cpu = smp_processor_id();
1581
1582 /*
1583 * We don't need to rewrite the page-tables if either we've done
1584 * it already or we have KASLR enabled and therefore have not
1585 * created any global mappings at all.
1586 */
1587 if (arm64_use_ng_mappings)
1588 return;
1589
1590 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1591
1592 cpu_install_idmap();
1593 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1594 cpu_uninstall_idmap();
1595
1596 if (!cpu)
1597 arm64_use_ng_mappings = true;
1598 }
1599 #else
1600 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1601 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1602 {
1603 }
1604 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1605
parse_kpti(char * str)1606 static int __init parse_kpti(char *str)
1607 {
1608 bool enabled;
1609 int ret = strtobool(str, &enabled);
1610
1611 if (ret)
1612 return ret;
1613
1614 __kpti_forced = enabled ? 1 : -1;
1615 return 0;
1616 }
1617 early_param("kpti", parse_kpti);
1618
1619 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1620 static inline void __cpu_enable_hw_dbm(void)
1621 {
1622 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1623
1624 write_sysreg(tcr, tcr_el1);
1625 isb();
1626 local_flush_tlb_all();
1627 }
1628
cpu_has_broken_dbm(void)1629 static bool cpu_has_broken_dbm(void)
1630 {
1631 /* List of CPUs which have broken DBM support. */
1632 static const struct midr_range cpus[] = {
1633 #ifdef CONFIG_ARM64_ERRATUM_1024718
1634 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1635 /* Kryo4xx Silver (rdpe => r1p0) */
1636 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1637 #endif
1638 {},
1639 };
1640
1641 return is_midr_in_range_list(read_cpuid_id(), cpus);
1642 }
1643
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1644 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1645 {
1646 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1647 !cpu_has_broken_dbm();
1648 }
1649
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1650 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1651 {
1652 if (cpu_can_use_dbm(cap))
1653 __cpu_enable_hw_dbm();
1654 }
1655
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1656 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1657 int __unused)
1658 {
1659 static bool detected = false;
1660 /*
1661 * DBM is a non-conflicting feature. i.e, the kernel can safely
1662 * run a mix of CPUs with and without the feature. So, we
1663 * unconditionally enable the capability to allow any late CPU
1664 * to use the feature. We only enable the control bits on the
1665 * CPU, if it actually supports.
1666 *
1667 * We have to make sure we print the "feature" detection only
1668 * when at least one CPU actually uses it. So check if this CPU
1669 * can actually use it and print the message exactly once.
1670 *
1671 * This is safe as all CPUs (including secondary CPUs - due to the
1672 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1673 * goes through the "matches" check exactly once. Also if a CPU
1674 * matches the criteria, it is guaranteed that the CPU will turn
1675 * the DBM on, as the capability is unconditionally enabled.
1676 */
1677 if (!detected && cpu_can_use_dbm(cap)) {
1678 detected = true;
1679 pr_info("detected: Hardware dirty bit management\n");
1680 }
1681
1682 return true;
1683 }
1684
1685 #endif
1686
1687 #ifdef CONFIG_ARM64_AMU_EXTN
1688
1689 /*
1690 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1691 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1692 * information regarding all the events that it supports. When a CPU bit is
1693 * set in the cpumask, the user of this feature can only rely on the presence
1694 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1695 * counters are enabled or access to these counters is enabled by code
1696 * executed at higher exception levels (firmware).
1697 */
1698 static struct cpumask amu_cpus __read_mostly;
1699
cpu_has_amu_feat(int cpu)1700 bool cpu_has_amu_feat(int cpu)
1701 {
1702 return cpumask_test_cpu(cpu, &amu_cpus);
1703 }
1704
get_cpu_with_amu_feat(void)1705 int get_cpu_with_amu_feat(void)
1706 {
1707 return cpumask_any(&amu_cpus);
1708 }
1709
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)1710 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1711 {
1712 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1713 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1714 smp_processor_id());
1715 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1716 update_freq_counters_refs();
1717 }
1718 }
1719
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)1720 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1721 int __unused)
1722 {
1723 /*
1724 * The AMU extension is a non-conflicting feature: the kernel can
1725 * safely run a mix of CPUs with and without support for the
1726 * activity monitors extension. Therefore, unconditionally enable
1727 * the capability to allow any late CPU to use the feature.
1728 *
1729 * With this feature unconditionally enabled, the cpu_enable
1730 * function will be called for all CPUs that match the criteria,
1731 * including secondary and hotplugged, marking this feature as
1732 * present on that respective CPU. The enable function will also
1733 * print a detection message.
1734 */
1735
1736 return true;
1737 }
1738 #else
get_cpu_with_amu_feat(void)1739 int get_cpu_with_amu_feat(void)
1740 {
1741 return nr_cpu_ids;
1742 }
1743 #endif
1744
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1745 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1746 {
1747 return is_kernel_in_hyp_mode();
1748 }
1749
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1750 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1751 {
1752 /*
1753 * Copy register values that aren't redirected by hardware.
1754 *
1755 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1756 * this value to tpidr_el2 before we patch the code. Once we've done
1757 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1758 * do anything here.
1759 */
1760 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1761 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1762 }
1763
cpu_has_fwb(const struct arm64_cpu_capabilities * __unused)1764 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1765 {
1766 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1767
1768 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1769 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val));
1770 }
1771
1772 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1773 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1774 {
1775 /*
1776 * We modify PSTATE. This won't work from irq context as the PSTATE
1777 * is discarded once we return from the exception.
1778 */
1779 WARN_ON_ONCE(in_interrupt());
1780
1781 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1782 set_pstate_pan(1);
1783 }
1784 #endif /* CONFIG_ARM64_PAN */
1785
1786 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1787 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1788 {
1789 /* Firmware may have left a deferred SError in this register. */
1790 write_sysreg_s(0, SYS_DISR_EL1);
1791 }
1792 #endif /* CONFIG_ARM64_RAS_EXTN */
1793
1794 #ifdef CONFIG_ARM64_PTR_AUTH
has_address_auth_cpucap(const struct arm64_cpu_capabilities * entry,int scope)1795 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1796 {
1797 int boot_val, sec_val;
1798
1799 /* We don't expect to be called with SCOPE_SYSTEM */
1800 WARN_ON(scope == SCOPE_SYSTEM);
1801 /*
1802 * The ptr-auth feature levels are not intercompatible with lower
1803 * levels. Hence we must match ptr-auth feature level of the secondary
1804 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1805 * from the sanitised register whereas direct register read is done for
1806 * the secondary CPUs.
1807 * The sanitised feature state is guaranteed to match that of the
1808 * boot CPU as a mismatched secondary CPU is parked before it gets
1809 * a chance to update the state, with the capability.
1810 */
1811 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1812 entry->field_pos, entry->sign);
1813 if (scope & SCOPE_BOOT_CPU)
1814 return boot_val >= entry->min_field_value;
1815 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1816 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1817 entry->field_pos, entry->sign);
1818 return sec_val == boot_val;
1819 }
1820
has_address_auth_metacap(const struct arm64_cpu_capabilities * entry,int scope)1821 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1822 int scope)
1823 {
1824 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1825 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1826 }
1827
has_generic_auth(const struct arm64_cpu_capabilities * entry,int __unused)1828 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1829 int __unused)
1830 {
1831 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1832 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1833 }
1834 #endif /* CONFIG_ARM64_PTR_AUTH */
1835
1836 #ifdef CONFIG_ARM64_E0PD
cpu_enable_e0pd(struct arm64_cpu_capabilities const * cap)1837 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1838 {
1839 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1840 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1841 }
1842 #endif /* CONFIG_ARM64_E0PD */
1843
1844 #ifdef CONFIG_ARM64_PSEUDO_NMI
1845 static bool enable_pseudo_nmi;
1846
early_enable_pseudo_nmi(char * p)1847 static int __init early_enable_pseudo_nmi(char *p)
1848 {
1849 return strtobool(p, &enable_pseudo_nmi);
1850 }
1851 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1852
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)1853 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1854 int scope)
1855 {
1856 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1857 }
1858 #endif
1859
1860 #ifdef CONFIG_ARM64_BTI
bti_enable(const struct arm64_cpu_capabilities * __unused)1861 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1862 {
1863 /*
1864 * Use of X16/X17 for tail-calls and trampolines that jump to
1865 * function entry points using BR is a requirement for
1866 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1867 * So, be strict and forbid other BRs using other registers to
1868 * jump onto a PACIxSP instruction:
1869 */
1870 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1871 isb();
1872 }
1873 #endif /* CONFIG_ARM64_BTI */
1874
1875 #ifdef CONFIG_ARM64_MTE
cpu_enable_mte(struct arm64_cpu_capabilities const * cap)1876 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1877 {
1878 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
1879 isb();
1880
1881 /*
1882 * Clear the tags in the zero page. This needs to be done via the
1883 * linear map which has the Tagged attribute.
1884 */
1885 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1886 mte_clear_page_tags(lm_alias(empty_zero_page));
1887
1888 kasan_init_hw_tags_cpu();
1889 }
1890 #endif /* CONFIG_ARM64_MTE */
1891
1892 #ifdef CONFIG_KVM
is_kvm_protected_mode(const struct arm64_cpu_capabilities * entry,int __unused)1893 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1894 {
1895 if (kvm_get_mode() != KVM_MODE_PROTECTED)
1896 return false;
1897
1898 if (is_kernel_in_hyp_mode()) {
1899 pr_warn("Protected KVM not available with VHE\n");
1900 return false;
1901 }
1902
1903 return true;
1904 }
1905 #endif /* CONFIG_KVM */
1906
1907 /* Internal helper functions to match cpu capability type */
1908 static bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)1909 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1910 {
1911 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1912 }
1913
1914 static bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)1915 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1916 {
1917 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1918 }
1919
1920 static bool
cpucap_panic_on_conflict(const struct arm64_cpu_capabilities * cap)1921 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1922 {
1923 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1924 }
1925
1926 static const struct arm64_cpu_capabilities arm64_features[] = {
1927 {
1928 .desc = "GIC system register CPU interface",
1929 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1930 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1931 .matches = has_useable_gicv3_cpuif,
1932 .sys_reg = SYS_ID_AA64PFR0_EL1,
1933 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1934 .sign = FTR_UNSIGNED,
1935 .min_field_value = 1,
1936 },
1937 {
1938 .desc = "Enhanced Counter Virtualization",
1939 .capability = ARM64_HAS_ECV,
1940 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1941 .matches = has_cpuid_feature,
1942 .sys_reg = SYS_ID_AA64MMFR0_EL1,
1943 .field_pos = ID_AA64MMFR0_ECV_SHIFT,
1944 .sign = FTR_UNSIGNED,
1945 .min_field_value = 1,
1946 },
1947 #ifdef CONFIG_ARM64_PAN
1948 {
1949 .desc = "Privileged Access Never",
1950 .capability = ARM64_HAS_PAN,
1951 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1952 .matches = has_cpuid_feature,
1953 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1954 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1955 .sign = FTR_UNSIGNED,
1956 .min_field_value = 1,
1957 .cpu_enable = cpu_enable_pan,
1958 },
1959 #endif /* CONFIG_ARM64_PAN */
1960 #ifdef CONFIG_ARM64_EPAN
1961 {
1962 .desc = "Enhanced Privileged Access Never",
1963 .capability = ARM64_HAS_EPAN,
1964 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1965 .matches = has_cpuid_feature,
1966 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1967 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1968 .sign = FTR_UNSIGNED,
1969 .min_field_value = 3,
1970 },
1971 #endif /* CONFIG_ARM64_EPAN */
1972 #ifdef CONFIG_ARM64_LSE_ATOMICS
1973 {
1974 .desc = "LSE atomic instructions",
1975 .capability = ARM64_HAS_LSE_ATOMICS,
1976 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1977 .matches = has_cpuid_feature,
1978 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1979 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1980 .sign = FTR_UNSIGNED,
1981 .min_field_value = 2,
1982 },
1983 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1984 {
1985 .desc = "Software prefetching using PRFM",
1986 .capability = ARM64_HAS_NO_HW_PREFETCH,
1987 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1988 .matches = has_no_hw_prefetch,
1989 },
1990 {
1991 .desc = "Virtualization Host Extensions",
1992 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1993 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1994 .matches = runs_at_el2,
1995 .cpu_enable = cpu_copy_el2regs,
1996 },
1997 {
1998 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
1999 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2000 .matches = has_32bit_el0,
2001 .sys_reg = SYS_ID_AA64PFR0_EL1,
2002 .sign = FTR_UNSIGNED,
2003 .field_pos = ID_AA64PFR0_EL0_SHIFT,
2004 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2005 },
2006 #ifdef CONFIG_KVM
2007 {
2008 .desc = "32-bit EL1 Support",
2009 .capability = ARM64_HAS_32BIT_EL1,
2010 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2011 .matches = has_cpuid_feature,
2012 .sys_reg = SYS_ID_AA64PFR0_EL1,
2013 .sign = FTR_UNSIGNED,
2014 .field_pos = ID_AA64PFR0_EL1_SHIFT,
2015 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2016 },
2017 {
2018 .desc = "Protected KVM",
2019 .capability = ARM64_KVM_PROTECTED_MODE,
2020 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2021 .matches = is_kvm_protected_mode,
2022 },
2023 #endif
2024 {
2025 .desc = "Kernel page table isolation (KPTI)",
2026 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2027 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2028 /*
2029 * The ID feature fields below are used to indicate that
2030 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2031 * more details.
2032 */
2033 .sys_reg = SYS_ID_AA64PFR0_EL1,
2034 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2035 .min_field_value = 1,
2036 .matches = unmap_kernel_at_el0,
2037 .cpu_enable = kpti_install_ng_mappings,
2038 },
2039 {
2040 /* FP/SIMD is not implemented */
2041 .capability = ARM64_HAS_NO_FPSIMD,
2042 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2043 .min_field_value = 0,
2044 .matches = has_no_fpsimd,
2045 },
2046 #ifdef CONFIG_ARM64_PMEM
2047 {
2048 .desc = "Data cache clean to Point of Persistence",
2049 .capability = ARM64_HAS_DCPOP,
2050 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2051 .matches = has_cpuid_feature,
2052 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2053 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2054 .min_field_value = 1,
2055 },
2056 {
2057 .desc = "Data cache clean to Point of Deep Persistence",
2058 .capability = ARM64_HAS_DCPODP,
2059 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2060 .matches = has_cpuid_feature,
2061 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2062 .sign = FTR_UNSIGNED,
2063 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2064 .min_field_value = 2,
2065 },
2066 #endif
2067 #ifdef CONFIG_ARM64_SVE
2068 {
2069 .desc = "Scalable Vector Extension",
2070 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2071 .capability = ARM64_SVE,
2072 .sys_reg = SYS_ID_AA64PFR0_EL1,
2073 .sign = FTR_UNSIGNED,
2074 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2075 .min_field_value = ID_AA64PFR0_SVE,
2076 .matches = has_cpuid_feature,
2077 .cpu_enable = sve_kernel_enable,
2078 },
2079 #endif /* CONFIG_ARM64_SVE */
2080 #ifdef CONFIG_ARM64_RAS_EXTN
2081 {
2082 .desc = "RAS Extension Support",
2083 .capability = ARM64_HAS_RAS_EXTN,
2084 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2085 .matches = has_cpuid_feature,
2086 .sys_reg = SYS_ID_AA64PFR0_EL1,
2087 .sign = FTR_UNSIGNED,
2088 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2089 .min_field_value = ID_AA64PFR0_RAS_V1,
2090 .cpu_enable = cpu_clear_disr,
2091 },
2092 #endif /* CONFIG_ARM64_RAS_EXTN */
2093 #ifdef CONFIG_ARM64_AMU_EXTN
2094 {
2095 /*
2096 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2097 * Therefore, don't provide .desc as we don't want the detection
2098 * message to be shown until at least one CPU is detected to
2099 * support the feature.
2100 */
2101 .capability = ARM64_HAS_AMU_EXTN,
2102 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2103 .matches = has_amu,
2104 .sys_reg = SYS_ID_AA64PFR0_EL1,
2105 .sign = FTR_UNSIGNED,
2106 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2107 .min_field_value = ID_AA64PFR0_AMU,
2108 .cpu_enable = cpu_amu_enable,
2109 },
2110 #endif /* CONFIG_ARM64_AMU_EXTN */
2111 {
2112 .desc = "Data cache clean to the PoU not required for I/D coherence",
2113 .capability = ARM64_HAS_CACHE_IDC,
2114 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2115 .matches = has_cache_idc,
2116 .cpu_enable = cpu_emulate_effective_ctr,
2117 },
2118 {
2119 .desc = "Instruction cache invalidation not required for I/D coherence",
2120 .capability = ARM64_HAS_CACHE_DIC,
2121 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2122 .matches = has_cache_dic,
2123 },
2124 {
2125 .desc = "Stage-2 Force Write-Back",
2126 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2127 .capability = ARM64_HAS_STAGE2_FWB,
2128 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2129 .sign = FTR_UNSIGNED,
2130 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2131 .min_field_value = 1,
2132 .matches = has_cpuid_feature,
2133 .cpu_enable = cpu_has_fwb,
2134 },
2135 {
2136 .desc = "ARMv8.4 Translation Table Level",
2137 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2138 .capability = ARM64_HAS_ARMv8_4_TTL,
2139 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2140 .sign = FTR_UNSIGNED,
2141 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2142 .min_field_value = 1,
2143 .matches = has_cpuid_feature,
2144 },
2145 {
2146 .desc = "TLB range maintenance instructions",
2147 .capability = ARM64_HAS_TLB_RANGE,
2148 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2149 .matches = has_cpuid_feature,
2150 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2151 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2152 .sign = FTR_UNSIGNED,
2153 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2154 },
2155 #ifdef CONFIG_ARM64_HW_AFDBM
2156 {
2157 /*
2158 * Since we turn this on always, we don't want the user to
2159 * think that the feature is available when it may not be.
2160 * So hide the description.
2161 *
2162 * .desc = "Hardware pagetable Dirty Bit Management",
2163 *
2164 */
2165 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2166 .capability = ARM64_HW_DBM,
2167 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2168 .sign = FTR_UNSIGNED,
2169 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2170 .min_field_value = 2,
2171 .matches = has_hw_dbm,
2172 .cpu_enable = cpu_enable_hw_dbm,
2173 },
2174 #endif
2175 {
2176 .desc = "CRC32 instructions",
2177 .capability = ARM64_HAS_CRC32,
2178 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2179 .matches = has_cpuid_feature,
2180 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2181 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2182 .min_field_value = 1,
2183 },
2184 {
2185 .desc = "Speculative Store Bypassing Safe (SSBS)",
2186 .capability = ARM64_SSBS,
2187 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2188 .matches = has_cpuid_feature,
2189 .sys_reg = SYS_ID_AA64PFR1_EL1,
2190 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2191 .sign = FTR_UNSIGNED,
2192 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2193 },
2194 #ifdef CONFIG_ARM64_CNP
2195 {
2196 .desc = "Common not Private translations",
2197 .capability = ARM64_HAS_CNP,
2198 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2199 .matches = has_useable_cnp,
2200 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2201 .sign = FTR_UNSIGNED,
2202 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2203 .min_field_value = 1,
2204 .cpu_enable = cpu_enable_cnp,
2205 },
2206 #endif
2207 {
2208 .desc = "Speculation barrier (SB)",
2209 .capability = ARM64_HAS_SB,
2210 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2211 .matches = has_cpuid_feature,
2212 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2213 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2214 .sign = FTR_UNSIGNED,
2215 .min_field_value = 1,
2216 },
2217 #ifdef CONFIG_ARM64_PTR_AUTH
2218 {
2219 .desc = "Address authentication (architected algorithm)",
2220 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2221 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2222 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2223 .sign = FTR_UNSIGNED,
2224 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2225 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2226 .matches = has_address_auth_cpucap,
2227 },
2228 {
2229 .desc = "Address authentication (IMP DEF algorithm)",
2230 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2231 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2232 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2233 .sign = FTR_UNSIGNED,
2234 .field_pos = ID_AA64ISAR1_API_SHIFT,
2235 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2236 .matches = has_address_auth_cpucap,
2237 },
2238 {
2239 .capability = ARM64_HAS_ADDRESS_AUTH,
2240 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2241 .matches = has_address_auth_metacap,
2242 },
2243 {
2244 .desc = "Generic authentication (architected algorithm)",
2245 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2246 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2247 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2248 .sign = FTR_UNSIGNED,
2249 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2250 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2251 .matches = has_cpuid_feature,
2252 },
2253 {
2254 .desc = "Generic authentication (IMP DEF algorithm)",
2255 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2256 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2257 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2258 .sign = FTR_UNSIGNED,
2259 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2260 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2261 .matches = has_cpuid_feature,
2262 },
2263 {
2264 .capability = ARM64_HAS_GENERIC_AUTH,
2265 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2266 .matches = has_generic_auth,
2267 },
2268 #endif /* CONFIG_ARM64_PTR_AUTH */
2269 #ifdef CONFIG_ARM64_PSEUDO_NMI
2270 {
2271 /*
2272 * Depends on having GICv3
2273 */
2274 .desc = "IRQ priority masking",
2275 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2276 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2277 .matches = can_use_gic_priorities,
2278 .sys_reg = SYS_ID_AA64PFR0_EL1,
2279 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2280 .sign = FTR_UNSIGNED,
2281 .min_field_value = 1,
2282 },
2283 #endif
2284 #ifdef CONFIG_ARM64_E0PD
2285 {
2286 .desc = "E0PD",
2287 .capability = ARM64_HAS_E0PD,
2288 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2289 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2290 .sign = FTR_UNSIGNED,
2291 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2292 .matches = has_cpuid_feature,
2293 .min_field_value = 1,
2294 .cpu_enable = cpu_enable_e0pd,
2295 },
2296 #endif
2297 #ifdef CONFIG_ARCH_RANDOM
2298 {
2299 .desc = "Random Number Generator",
2300 .capability = ARM64_HAS_RNG,
2301 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2302 .matches = has_cpuid_feature,
2303 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2304 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2305 .sign = FTR_UNSIGNED,
2306 .min_field_value = 1,
2307 },
2308 #endif
2309 #ifdef CONFIG_ARM64_BTI
2310 {
2311 .desc = "Branch Target Identification",
2312 .capability = ARM64_BTI,
2313 #ifdef CONFIG_ARM64_BTI_KERNEL
2314 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2315 #else
2316 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2317 #endif
2318 .matches = has_cpuid_feature,
2319 .cpu_enable = bti_enable,
2320 .sys_reg = SYS_ID_AA64PFR1_EL1,
2321 .field_pos = ID_AA64PFR1_BT_SHIFT,
2322 .min_field_value = ID_AA64PFR1_BT_BTI,
2323 .sign = FTR_UNSIGNED,
2324 },
2325 #endif
2326 #ifdef CONFIG_ARM64_MTE
2327 {
2328 .desc = "Memory Tagging Extension",
2329 .capability = ARM64_MTE,
2330 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2331 .matches = has_cpuid_feature,
2332 .sys_reg = SYS_ID_AA64PFR1_EL1,
2333 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2334 .min_field_value = ID_AA64PFR1_MTE,
2335 .sign = FTR_UNSIGNED,
2336 .cpu_enable = cpu_enable_mte,
2337 },
2338 {
2339 .desc = "Asymmetric MTE Tag Check Fault",
2340 .capability = ARM64_MTE_ASYMM,
2341 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2342 .matches = has_cpuid_feature,
2343 .sys_reg = SYS_ID_AA64PFR1_EL1,
2344 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2345 .min_field_value = ID_AA64PFR1_MTE_ASYMM,
2346 .sign = FTR_UNSIGNED,
2347 },
2348 #endif /* CONFIG_ARM64_MTE */
2349 {
2350 .desc = "RCpc load-acquire (LDAPR)",
2351 .capability = ARM64_HAS_LDAPR,
2352 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2353 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2354 .sign = FTR_UNSIGNED,
2355 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2356 .matches = has_cpuid_feature,
2357 .min_field_value = 1,
2358 },
2359 {},
2360 };
2361
2362 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2363 .matches = has_cpuid_feature, \
2364 .sys_reg = reg, \
2365 .field_pos = field, \
2366 .sign = s, \
2367 .min_field_value = min_value,
2368
2369 #define __HWCAP_CAP(name, cap_type, cap) \
2370 .desc = name, \
2371 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2372 .hwcap_type = cap_type, \
2373 .hwcap = cap, \
2374
2375 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2376 { \
2377 __HWCAP_CAP(#cap, cap_type, cap) \
2378 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2379 }
2380
2381 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2382 { \
2383 __HWCAP_CAP(#cap, cap_type, cap) \
2384 .matches = cpucap_multi_entry_cap_matches, \
2385 .match_list = list, \
2386 }
2387
2388 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2389 { \
2390 __HWCAP_CAP(#cap, cap_type, cap) \
2391 .matches = match, \
2392 }
2393
2394 #ifdef CONFIG_ARM64_PTR_AUTH
2395 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2396 {
2397 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2398 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2399 },
2400 {
2401 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2402 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2403 },
2404 {},
2405 };
2406
2407 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2408 {
2409 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2410 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2411 },
2412 {
2413 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2414 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2415 },
2416 {},
2417 };
2418 #endif
2419
2420 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2421 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2422 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2423 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2424 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2425 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2426 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2427 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2428 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2429 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2430 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2431 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2432 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2433 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2434 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2435 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2436 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2437 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2438 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2439 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2440 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2441 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2442 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2443 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2444 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2445 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2446 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2447 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2448 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2449 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2450 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2451 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2452 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2453 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2454 #ifdef CONFIG_ARM64_SVE
2455 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2456 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2457 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2458 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2459 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2460 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2461 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2462 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2463 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2464 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2465 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2466 #endif
2467 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2468 #ifdef CONFIG_ARM64_BTI
2469 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2470 #endif
2471 #ifdef CONFIG_ARM64_PTR_AUTH
2472 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2473 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2474 #endif
2475 #ifdef CONFIG_ARM64_MTE
2476 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2477 #endif /* CONFIG_ARM64_MTE */
2478 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2479 {},
2480 };
2481
2482 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)2483 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2484 {
2485 /*
2486 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2487 * in line with that of arm32 as in vfp_init(). We make sure that the
2488 * check is future proof, by making sure value is non-zero.
2489 */
2490 u32 mvfr1;
2491
2492 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2493 if (scope == SCOPE_SYSTEM)
2494 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2495 else
2496 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2497
2498 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2499 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2500 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2501 }
2502 #endif
2503
2504 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2505 #ifdef CONFIG_COMPAT
2506 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2507 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2508 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2509 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2510 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2511 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2512 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2513 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2514 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2515 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2516 #endif
2517 {},
2518 };
2519
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)2520 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2521 {
2522 switch (cap->hwcap_type) {
2523 case CAP_HWCAP:
2524 cpu_set_feature(cap->hwcap);
2525 break;
2526 #ifdef CONFIG_COMPAT
2527 case CAP_COMPAT_HWCAP:
2528 compat_elf_hwcap |= (u32)cap->hwcap;
2529 break;
2530 case CAP_COMPAT_HWCAP2:
2531 compat_elf_hwcap2 |= (u32)cap->hwcap;
2532 break;
2533 #endif
2534 default:
2535 WARN_ON(1);
2536 break;
2537 }
2538 }
2539
2540 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)2541 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2542 {
2543 bool rc;
2544
2545 switch (cap->hwcap_type) {
2546 case CAP_HWCAP:
2547 rc = cpu_have_feature(cap->hwcap);
2548 break;
2549 #ifdef CONFIG_COMPAT
2550 case CAP_COMPAT_HWCAP:
2551 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2552 break;
2553 case CAP_COMPAT_HWCAP2:
2554 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2555 break;
2556 #endif
2557 default:
2558 WARN_ON(1);
2559 rc = false;
2560 }
2561
2562 return rc;
2563 }
2564
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)2565 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2566 {
2567 /* We support emulation of accesses to CPU ID feature registers */
2568 cpu_set_named_feature(CPUID);
2569 for (; hwcaps->matches; hwcaps++)
2570 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2571 cap_set_elf_hwcap(hwcaps);
2572 }
2573
update_cpu_capabilities(u16 scope_mask)2574 static void update_cpu_capabilities(u16 scope_mask)
2575 {
2576 int i;
2577 const struct arm64_cpu_capabilities *caps;
2578
2579 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2580 for (i = 0; i < ARM64_NCAPS; i++) {
2581 caps = cpu_hwcaps_ptrs[i];
2582 if (!caps || !(caps->type & scope_mask) ||
2583 cpus_have_cap(caps->capability) ||
2584 !caps->matches(caps, cpucap_default_scope(caps)))
2585 continue;
2586
2587 if (caps->desc)
2588 pr_info("detected: %s\n", caps->desc);
2589 cpus_set_cap(caps->capability);
2590
2591 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2592 set_bit(caps->capability, boot_capabilities);
2593 }
2594 }
2595
2596 /*
2597 * Enable all the available capabilities on this CPU. The capabilities
2598 * with BOOT_CPU scope are handled separately and hence skipped here.
2599 */
cpu_enable_non_boot_scope_capabilities(void * __unused)2600 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2601 {
2602 int i;
2603 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2604
2605 for_each_available_cap(i) {
2606 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2607
2608 if (WARN_ON(!cap))
2609 continue;
2610
2611 if (!(cap->type & non_boot_scope))
2612 continue;
2613
2614 if (cap->cpu_enable)
2615 cap->cpu_enable(cap);
2616 }
2617 return 0;
2618 }
2619
2620 /*
2621 * Run through the enabled capabilities and enable() it on all active
2622 * CPUs
2623 */
enable_cpu_capabilities(u16 scope_mask)2624 static void __init enable_cpu_capabilities(u16 scope_mask)
2625 {
2626 int i;
2627 const struct arm64_cpu_capabilities *caps;
2628 bool boot_scope;
2629
2630 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2631 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2632
2633 for (i = 0; i < ARM64_NCAPS; i++) {
2634 unsigned int num;
2635
2636 caps = cpu_hwcaps_ptrs[i];
2637 if (!caps || !(caps->type & scope_mask))
2638 continue;
2639 num = caps->capability;
2640 if (!cpus_have_cap(num))
2641 continue;
2642
2643 /* Ensure cpus_have_const_cap(num) works */
2644 static_branch_enable(&cpu_hwcap_keys[num]);
2645
2646 if (boot_scope && caps->cpu_enable)
2647 /*
2648 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2649 * before any secondary CPU boots. Thus, each secondary
2650 * will enable the capability as appropriate via
2651 * check_local_cpu_capabilities(). The only exception is
2652 * the boot CPU, for which the capability must be
2653 * enabled here. This approach avoids costly
2654 * stop_machine() calls for this case.
2655 */
2656 caps->cpu_enable(caps);
2657 }
2658
2659 /*
2660 * For all non-boot scope capabilities, use stop_machine()
2661 * as it schedules the work allowing us to modify PSTATE,
2662 * instead of on_each_cpu() which uses an IPI, giving us a
2663 * PSTATE that disappears when we return.
2664 */
2665 if (!boot_scope)
2666 stop_machine(cpu_enable_non_boot_scope_capabilities,
2667 NULL, cpu_online_mask);
2668 }
2669
2670 /*
2671 * Run through the list of capabilities to check for conflicts.
2672 * If the system has already detected a capability, take necessary
2673 * action on this CPU.
2674 */
verify_local_cpu_caps(u16 scope_mask)2675 static void verify_local_cpu_caps(u16 scope_mask)
2676 {
2677 int i;
2678 bool cpu_has_cap, system_has_cap;
2679 const struct arm64_cpu_capabilities *caps;
2680
2681 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2682
2683 for (i = 0; i < ARM64_NCAPS; i++) {
2684 caps = cpu_hwcaps_ptrs[i];
2685 if (!caps || !(caps->type & scope_mask))
2686 continue;
2687
2688 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2689 system_has_cap = cpus_have_cap(caps->capability);
2690
2691 if (system_has_cap) {
2692 /*
2693 * Check if the new CPU misses an advertised feature,
2694 * which is not safe to miss.
2695 */
2696 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2697 break;
2698 /*
2699 * We have to issue cpu_enable() irrespective of
2700 * whether the CPU has it or not, as it is enabeld
2701 * system wide. It is upto the call back to take
2702 * appropriate action on this CPU.
2703 */
2704 if (caps->cpu_enable)
2705 caps->cpu_enable(caps);
2706 } else {
2707 /*
2708 * Check if the CPU has this capability if it isn't
2709 * safe to have when the system doesn't.
2710 */
2711 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2712 break;
2713 }
2714 }
2715
2716 if (i < ARM64_NCAPS) {
2717 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2718 smp_processor_id(), caps->capability,
2719 caps->desc, system_has_cap, cpu_has_cap);
2720
2721 if (cpucap_panic_on_conflict(caps))
2722 cpu_panic_kernel();
2723 else
2724 cpu_die_early();
2725 }
2726 }
2727
2728 /*
2729 * Check for CPU features that are used in early boot
2730 * based on the Boot CPU value.
2731 */
check_early_cpu_features(void)2732 static void check_early_cpu_features(void)
2733 {
2734 verify_cpu_asid_bits();
2735
2736 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2737 }
2738
2739 static void
__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)2740 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2741 {
2742
2743 for (; caps->matches; caps++)
2744 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2745 pr_crit("CPU%d: missing HWCAP: %s\n",
2746 smp_processor_id(), caps->desc);
2747 cpu_die_early();
2748 }
2749 }
2750
verify_local_elf_hwcaps(void)2751 static void verify_local_elf_hwcaps(void)
2752 {
2753 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2754
2755 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2756 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2757 }
2758
verify_sve_features(void)2759 static void verify_sve_features(void)
2760 {
2761 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2762 u64 zcr = read_zcr_features();
2763
2764 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2765 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2766
2767 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
2768 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2769 smp_processor_id());
2770 cpu_die_early();
2771 }
2772
2773 /* Add checks on other ZCR bits here if necessary */
2774 }
2775
verify_hyp_capabilities(void)2776 static void verify_hyp_capabilities(void)
2777 {
2778 u64 safe_mmfr1, mmfr0, mmfr1;
2779 int parange, ipa_max;
2780 unsigned int safe_vmid_bits, vmid_bits;
2781
2782 if (!IS_ENABLED(CONFIG_KVM))
2783 return;
2784
2785 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2786 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2787 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2788
2789 /* Verify VMID bits */
2790 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2791 vmid_bits = get_vmid_bits(mmfr1);
2792 if (vmid_bits < safe_vmid_bits) {
2793 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2794 cpu_die_early();
2795 }
2796
2797 /* Verify IPA range */
2798 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2799 ID_AA64MMFR0_PARANGE_SHIFT);
2800 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2801 if (ipa_max < get_kvm_ipa_limit()) {
2802 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2803 cpu_die_early();
2804 }
2805 }
2806
2807 /*
2808 * Run through the enabled system capabilities and enable() it on this CPU.
2809 * The capabilities were decided based on the available CPUs at the boot time.
2810 * Any new CPU should match the system wide status of the capability. If the
2811 * new CPU doesn't have a capability which the system now has enabled, we
2812 * cannot do anything to fix it up and could cause unexpected failures. So
2813 * we park the CPU.
2814 */
verify_local_cpu_capabilities(void)2815 static void verify_local_cpu_capabilities(void)
2816 {
2817 /*
2818 * The capabilities with SCOPE_BOOT_CPU are checked from
2819 * check_early_cpu_features(), as they need to be verified
2820 * on all secondary CPUs.
2821 */
2822 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2823 verify_local_elf_hwcaps();
2824
2825 if (system_supports_sve())
2826 verify_sve_features();
2827
2828 if (is_hyp_mode_available())
2829 verify_hyp_capabilities();
2830 }
2831
check_local_cpu_capabilities(void)2832 void check_local_cpu_capabilities(void)
2833 {
2834 /*
2835 * All secondary CPUs should conform to the early CPU features
2836 * in use by the kernel based on boot CPU.
2837 */
2838 check_early_cpu_features();
2839
2840 /*
2841 * If we haven't finalised the system capabilities, this CPU gets
2842 * a chance to update the errata work arounds and local features.
2843 * Otherwise, this CPU should verify that it has all the system
2844 * advertised capabilities.
2845 */
2846 if (!system_capabilities_finalized())
2847 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2848 else
2849 verify_local_cpu_capabilities();
2850 }
2851
setup_boot_cpu_capabilities(void)2852 static void __init setup_boot_cpu_capabilities(void)
2853 {
2854 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2855 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2856 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2857 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2858 }
2859
this_cpu_has_cap(unsigned int n)2860 bool this_cpu_has_cap(unsigned int n)
2861 {
2862 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2863 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2864
2865 if (cap)
2866 return cap->matches(cap, SCOPE_LOCAL_CPU);
2867 }
2868
2869 return false;
2870 }
2871 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
2872
2873 /*
2874 * This helper function is used in a narrow window when,
2875 * - The system wide safe registers are set with all the SMP CPUs and,
2876 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2877 * In all other cases cpus_have_{const_}cap() should be used.
2878 */
__system_matches_cap(unsigned int n)2879 static bool __maybe_unused __system_matches_cap(unsigned int n)
2880 {
2881 if (n < ARM64_NCAPS) {
2882 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2883
2884 if (cap)
2885 return cap->matches(cap, SCOPE_SYSTEM);
2886 }
2887 return false;
2888 }
2889
cpu_set_feature(unsigned int num)2890 void cpu_set_feature(unsigned int num)
2891 {
2892 WARN_ON(num >= MAX_CPU_FEATURES);
2893 elf_hwcap |= BIT(num);
2894 }
2895 EXPORT_SYMBOL_GPL(cpu_set_feature);
2896
cpu_have_feature(unsigned int num)2897 bool cpu_have_feature(unsigned int num)
2898 {
2899 WARN_ON(num >= MAX_CPU_FEATURES);
2900 return elf_hwcap & BIT(num);
2901 }
2902 EXPORT_SYMBOL_GPL(cpu_have_feature);
2903
cpu_get_elf_hwcap(void)2904 unsigned long cpu_get_elf_hwcap(void)
2905 {
2906 /*
2907 * We currently only populate the first 32 bits of AT_HWCAP. Please
2908 * note that for userspace compatibility we guarantee that bits 62
2909 * and 63 will always be returned as 0.
2910 */
2911 return lower_32_bits(elf_hwcap);
2912 }
2913
cpu_get_elf_hwcap2(void)2914 unsigned long cpu_get_elf_hwcap2(void)
2915 {
2916 return upper_32_bits(elf_hwcap);
2917 }
2918
setup_system_capabilities(void)2919 static void __init setup_system_capabilities(void)
2920 {
2921 /*
2922 * We have finalised the system-wide safe feature
2923 * registers, finalise the capabilities that depend
2924 * on it. Also enable all the available capabilities,
2925 * that are not enabled already.
2926 */
2927 update_cpu_capabilities(SCOPE_SYSTEM);
2928 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2929 }
2930
setup_cpu_features(void)2931 void __init setup_cpu_features(void)
2932 {
2933 u32 cwg;
2934
2935 setup_system_capabilities();
2936 setup_elf_hwcaps(arm64_elf_hwcaps);
2937
2938 if (system_supports_32bit_el0())
2939 setup_elf_hwcaps(compat_elf_hwcaps);
2940
2941 if (system_uses_ttbr0_pan())
2942 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2943
2944 sve_setup();
2945 minsigstksz_setup();
2946
2947 /* Advertise that we have computed the system capabilities */
2948 finalize_system_capabilities();
2949
2950 /*
2951 * Check for sane CTR_EL0.CWG value.
2952 */
2953 cwg = cache_type_cwg();
2954 if (!cwg)
2955 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2956 ARCH_DMA_MINALIGN);
2957 }
2958
enable_mismatched_32bit_el0(unsigned int cpu)2959 static int enable_mismatched_32bit_el0(unsigned int cpu)
2960 {
2961 /*
2962 * The first 32-bit-capable CPU we detected and so can no longer
2963 * be offlined by userspace. -1 indicates we haven't yet onlined
2964 * a 32-bit-capable CPU.
2965 */
2966 static int lucky_winner = -1;
2967
2968 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
2969 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
2970
2971 if (cpu_32bit) {
2972 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
2973 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
2974 }
2975
2976 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
2977 return 0;
2978
2979 if (lucky_winner >= 0)
2980 return 0;
2981
2982 /*
2983 * We've detected a mismatch. We need to keep one of our CPUs with
2984 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
2985 * every CPU in the system for a 32-bit task.
2986 */
2987 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
2988 cpu_active_mask);
2989 get_cpu_device(lucky_winner)->offline_disabled = true;
2990 setup_elf_hwcaps(compat_elf_hwcaps);
2991 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
2992 cpu, lucky_winner);
2993 return 0;
2994 }
2995
init_32bit_el0_mask(void)2996 static int __init init_32bit_el0_mask(void)
2997 {
2998 if (!allow_mismatched_32bit_el0)
2999 return 0;
3000
3001 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3002 return -ENOMEM;
3003
3004 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3005 "arm64/mismatched_32bit_el0:online",
3006 enable_mismatched_32bit_el0, NULL);
3007 }
3008 subsys_initcall_sync(init_32bit_el0_mask);
3009
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)3010 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3011 {
3012 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
3013 }
3014
3015 /*
3016 * We emulate only the following system register space.
3017 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
3018 * See Table C5-6 System instruction encodings for System register accesses,
3019 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3020 */
is_emulated(u32 id)3021 static inline bool __attribute_const__ is_emulated(u32 id)
3022 {
3023 return (sys_reg_Op0(id) == 0x3 &&
3024 sys_reg_CRn(id) == 0x0 &&
3025 sys_reg_Op1(id) == 0x0 &&
3026 (sys_reg_CRm(id) == 0 ||
3027 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3028 }
3029
3030 /*
3031 * With CRm == 0, reg should be one of :
3032 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3033 */
emulate_id_reg(u32 id,u64 * valp)3034 static inline int emulate_id_reg(u32 id, u64 *valp)
3035 {
3036 switch (id) {
3037 case SYS_MIDR_EL1:
3038 *valp = read_cpuid_id();
3039 break;
3040 case SYS_MPIDR_EL1:
3041 *valp = SYS_MPIDR_SAFE_VAL;
3042 break;
3043 case SYS_REVIDR_EL1:
3044 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3045 *valp = 0;
3046 break;
3047 default:
3048 return -EINVAL;
3049 }
3050
3051 return 0;
3052 }
3053
emulate_sys_reg(u32 id,u64 * valp)3054 static int emulate_sys_reg(u32 id, u64 *valp)
3055 {
3056 struct arm64_ftr_reg *regp;
3057
3058 if (!is_emulated(id))
3059 return -EINVAL;
3060
3061 if (sys_reg_CRm(id) == 0)
3062 return emulate_id_reg(id, valp);
3063
3064 regp = get_arm64_ftr_reg_nowarn(id);
3065 if (regp)
3066 *valp = arm64_ftr_reg_user_value(regp);
3067 else
3068 /*
3069 * The untracked registers are either IMPLEMENTATION DEFINED
3070 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3071 */
3072 *valp = 0;
3073 return 0;
3074 }
3075
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)3076 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3077 {
3078 int rc;
3079 u64 val;
3080
3081 rc = emulate_sys_reg(sys_reg, &val);
3082 if (!rc) {
3083 pt_regs_write_reg(regs, rt, val);
3084 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3085 }
3086 return rc;
3087 }
3088
emulate_mrs(struct pt_regs * regs,u32 insn)3089 static int emulate_mrs(struct pt_regs *regs, u32 insn)
3090 {
3091 u32 sys_reg, rt;
3092
3093 /*
3094 * sys_reg values are defined as used in mrs/msr instruction.
3095 * shift the imm value to get the encoding.
3096 */
3097 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3098 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3099 return do_emulate_mrs(regs, sys_reg, rt);
3100 }
3101
3102 static struct undef_hook mrs_hook = {
3103 .instr_mask = 0xffff0000,
3104 .instr_val = 0xd5380000,
3105 .pstate_mask = PSR_AA32_MODE_MASK,
3106 .pstate_val = PSR_MODE_EL0t,
3107 .fn = emulate_mrs,
3108 };
3109
enable_mrs_emulation(void)3110 static int __init enable_mrs_emulation(void)
3111 {
3112 register_undef_hook(&mrs_hook);
3113 return 0;
3114 }
3115
3116 core_initcall(enable_mrs_emulation);
3117
arm64_get_meltdown_state(void)3118 enum mitigation_state arm64_get_meltdown_state(void)
3119 {
3120 if (__meltdown_safe)
3121 return SPECTRE_UNAFFECTED;
3122
3123 if (arm64_kernel_unmapped_at_el0())
3124 return SPECTRE_MITIGATED;
3125
3126 return SPECTRE_VULNERABLE;
3127 }
3128
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)3129 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3130 char *buf)
3131 {
3132 switch (arm64_get_meltdown_state()) {
3133 case SPECTRE_UNAFFECTED:
3134 return sprintf(buf, "Not affected\n");
3135
3136 case SPECTRE_MITIGATED:
3137 return sprintf(buf, "Mitigation: PTI\n");
3138
3139 default:
3140 return sprintf(buf, "Vulnerable\n");
3141 }
3142 }
3143