1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "reg_helper.h"
29 #include "dce_audio.h"
30 #include "dce/dce_11_0_d.h"
31 #include "dce/dce_11_0_sh_mask.h"
32
33 #define DCE_AUD(audio)\
34 container_of(audio, struct dce_audio, base)
35
36 #define CTX \
37 aud->base.ctx
38
39 #define DC_LOGGER_INIT()
40
41 #define REG(reg)\
42 (aud->regs->reg)
43
44 #undef FN
45 #define FN(reg_name, field_name) \
46 aud->shifts->field_name, aud->masks->field_name
47
48 #define IX_REG(reg)\
49 ix ## reg
50
51 #define AZ_REG_READ(reg_name) \
52 read_indirect_azalia_reg(audio, IX_REG(reg_name))
53
54 #define AZ_REG_WRITE(reg_name, value) \
55 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
56
write_indirect_azalia_reg(struct audio * audio,uint32_t reg_index,uint32_t reg_data)57 static void write_indirect_azalia_reg(struct audio *audio,
58 uint32_t reg_index,
59 uint32_t reg_data)
60 {
61 struct dce_audio *aud = DCE_AUD(audio);
62
63 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
64 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
65 AZALIA_ENDPOINT_REG_INDEX, reg_index);
66
67 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
68 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
69 AZALIA_ENDPOINT_REG_DATA, reg_data);
70
71 DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
72 reg_index, reg_data);
73 }
74
read_indirect_azalia_reg(struct audio * audio,uint32_t reg_index)75 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
76 {
77 struct dce_audio *aud = DCE_AUD(audio);
78
79 uint32_t value = 0;
80
81 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
82 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
83 AZALIA_ENDPOINT_REG_INDEX, reg_index);
84
85 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
86 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
87
88 DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
89 reg_index, value);
90
91 return value;
92 }
93
is_audio_format_supported(const struct audio_info * audio_info,enum audio_format_code audio_format_code,uint32_t * format_index)94 static bool is_audio_format_supported(
95 const struct audio_info *audio_info,
96 enum audio_format_code audio_format_code,
97 uint32_t *format_index)
98 {
99 uint32_t index;
100 uint32_t max_channe_index = 0;
101 bool found = false;
102
103 if (audio_info == NULL)
104 return found;
105
106 /* pass through whole array */
107 for (index = 0; index < audio_info->mode_count; index++) {
108 if (audio_info->modes[index].format_code == audio_format_code) {
109 if (found) {
110 /* format has multiply entries, choose one with
111 * highst number of channels */
112 if (audio_info->modes[index].channel_count >
113 audio_info->modes[max_channe_index].channel_count) {
114 max_channe_index = index;
115 }
116 } else {
117 /* format found, save it's index */
118 found = true;
119 max_channe_index = index;
120 }
121 }
122 }
123
124 /* return index */
125 if (found && format_index != NULL)
126 *format_index = max_channe_index;
127
128 return found;
129 }
130
131 /*For HDMI, calculate if specified sample rates can fit into a given timing */
check_audio_bandwidth_hdmi(const struct audio_crtc_info * crtc_info,uint32_t channel_count,union audio_sample_rates * sample_rates)132 static void check_audio_bandwidth_hdmi(
133 const struct audio_crtc_info *crtc_info,
134 uint32_t channel_count,
135 union audio_sample_rates *sample_rates)
136 {
137 uint32_t samples;
138 uint32_t h_blank;
139 bool limit_freq_to_48_khz = false;
140 bool limit_freq_to_88_2_khz = false;
141 bool limit_freq_to_96_khz = false;
142 bool limit_freq_to_174_4_khz = false;
143 if (!crtc_info)
144 return;
145
146 /* For two channels supported return whatever sink support,unmodified*/
147 if (channel_count > 2) {
148
149 /* Based on HDMI spec 1.3 Table 7.5 */
150 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
151 (crtc_info->v_active <= 576) &&
152 !(crtc_info->interlaced) &&
153 !(crtc_info->pixel_repetition == 2 ||
154 crtc_info->pixel_repetition == 4)) {
155 limit_freq_to_48_khz = true;
156
157 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
158 (crtc_info->v_active <= 576) &&
159 (crtc_info->interlaced) &&
160 (crtc_info->pixel_repetition == 2)) {
161 limit_freq_to_88_2_khz = true;
162
163 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
164 (crtc_info->v_active <= 576) &&
165 !(crtc_info->interlaced)) {
166 limit_freq_to_174_4_khz = true;
167 }
168 }
169
170 /* Also do some calculation for the available Audio Bandwidth for the
171 * 8 ch (i.e. for the Layout 1 => ch > 2)
172 */
173 h_blank = crtc_info->h_total - crtc_info->h_active;
174
175 if (crtc_info->pixel_repetition)
176 h_blank *= crtc_info->pixel_repetition;
177
178 /*based on HDMI spec 1.3 Table 7.5 */
179 h_blank -= 58;
180 /*for Control Period */
181 h_blank -= 16;
182
183 samples = h_blank * 10;
184 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
185 * of Audio samples per line multiplied by 10 - Layout 1)
186 */
187 samples /= 32;
188 samples *= crtc_info->v_active;
189 /*Number of samples multiplied by 10, per second */
190 samples *= crtc_info->refresh_rate;
191 /*Number of Audio samples per second */
192 samples /= 10;
193
194 /* @todo do it after deep color is implemented
195 * 8xx - deep color bandwidth scaling
196 * Extra bandwidth is avaliable in deep color b/c link runs faster than
197 * pixel rate. This has the effect of allowing more tmds characters to
198 * be transmitted during blank
199 */
200
201 switch (crtc_info->color_depth) {
202 case COLOR_DEPTH_888:
203 samples *= 4;
204 break;
205 case COLOR_DEPTH_101010:
206 samples *= 5;
207 break;
208 case COLOR_DEPTH_121212:
209 samples *= 6;
210 break;
211 default:
212 samples *= 4;
213 break;
214 }
215
216 samples /= 4;
217
218 /*check limitation*/
219 if (samples < 88200)
220 limit_freq_to_48_khz = true;
221 else if (samples < 96000)
222 limit_freq_to_88_2_khz = true;
223 else if (samples < 176400)
224 limit_freq_to_96_khz = true;
225 else if (samples < 192000)
226 limit_freq_to_174_4_khz = true;
227
228 if (sample_rates != NULL) {
229 /* limit frequencies */
230 if (limit_freq_to_174_4_khz)
231 sample_rates->rate.RATE_192 = 0;
232
233 if (limit_freq_to_96_khz) {
234 sample_rates->rate.RATE_192 = 0;
235 sample_rates->rate.RATE_176_4 = 0;
236 }
237 if (limit_freq_to_88_2_khz) {
238 sample_rates->rate.RATE_192 = 0;
239 sample_rates->rate.RATE_176_4 = 0;
240 sample_rates->rate.RATE_96 = 0;
241 }
242 if (limit_freq_to_48_khz) {
243 sample_rates->rate.RATE_192 = 0;
244 sample_rates->rate.RATE_176_4 = 0;
245 sample_rates->rate.RATE_96 = 0;
246 sample_rates->rate.RATE_88_2 = 0;
247 }
248 }
249 }
250
251 /*For DP SST, calculate if specified sample rates can fit into a given timing */
check_audio_bandwidth_dpsst(const struct audio_crtc_info * crtc_info,uint32_t channel_count,union audio_sample_rates * sample_rates)252 static void check_audio_bandwidth_dpsst(
253 const struct audio_crtc_info *crtc_info,
254 uint32_t channel_count,
255 union audio_sample_rates *sample_rates)
256 {
257 /* do nothing */
258 }
259
260 /*For DP MST, calculate if specified sample rates can fit into a given timing */
check_audio_bandwidth_dpmst(const struct audio_crtc_info * crtc_info,uint32_t channel_count,union audio_sample_rates * sample_rates)261 static void check_audio_bandwidth_dpmst(
262 const struct audio_crtc_info *crtc_info,
263 uint32_t channel_count,
264 union audio_sample_rates *sample_rates)
265 {
266 /* do nothing */
267 }
268
check_audio_bandwidth(const struct audio_crtc_info * crtc_info,uint32_t channel_count,enum signal_type signal,union audio_sample_rates * sample_rates)269 static void check_audio_bandwidth(
270 const struct audio_crtc_info *crtc_info,
271 uint32_t channel_count,
272 enum signal_type signal,
273 union audio_sample_rates *sample_rates)
274 {
275 switch (signal) {
276 case SIGNAL_TYPE_HDMI_TYPE_A:
277 check_audio_bandwidth_hdmi(
278 crtc_info, channel_count, sample_rates);
279 break;
280 case SIGNAL_TYPE_EDP:
281 case SIGNAL_TYPE_DISPLAY_PORT:
282 check_audio_bandwidth_dpsst(
283 crtc_info, channel_count, sample_rates);
284 break;
285 case SIGNAL_TYPE_DISPLAY_PORT_MST:
286 check_audio_bandwidth_dpmst(
287 crtc_info, channel_count, sample_rates);
288 break;
289 default:
290 break;
291 }
292 }
293
294 /* expose/not expose HBR capability to Audio driver */
set_high_bit_rate_capable(struct audio * audio,bool capable)295 static void set_high_bit_rate_capable(
296 struct audio *audio,
297 bool capable)
298 {
299 uint32_t value = 0;
300
301 /* set high bit rate audio capable*/
302 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
303
304 set_reg_field_value(value, capable,
305 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
306 HBR_CAPABLE);
307
308 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
309 }
310
311 /* set video latency in in ms/2+1 */
set_video_latency(struct audio * audio,int latency_in_ms)312 static void set_video_latency(
313 struct audio *audio,
314 int latency_in_ms)
315 {
316 uint32_t value = 0;
317
318 if ((latency_in_ms < 0) || (latency_in_ms > 255))
319 return;
320
321 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
322
323 set_reg_field_value(value, latency_in_ms,
324 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
325 VIDEO_LIPSYNC);
326
327 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
328 value);
329 }
330
331 /* set audio latency in in ms/2+1 */
set_audio_latency(struct audio * audio,int latency_in_ms)332 static void set_audio_latency(
333 struct audio *audio,
334 int latency_in_ms)
335 {
336 uint32_t value = 0;
337
338 if (latency_in_ms < 0)
339 latency_in_ms = 0;
340
341 if (latency_in_ms > 255)
342 latency_in_ms = 255;
343
344 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
345
346 set_reg_field_value(value, latency_in_ms,
347 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
348 AUDIO_LIPSYNC);
349
350 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
351 value);
352 }
353
dce_aud_az_enable(struct audio * audio)354 void dce_aud_az_enable(struct audio *audio)
355 {
356 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
357 DC_LOGGER_INIT();
358
359 set_reg_field_value(value, 1,
360 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
361 CLOCK_GATING_DISABLE);
362 set_reg_field_value(value, 1,
363 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
364 AUDIO_ENABLED);
365
366 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
367 set_reg_field_value(value, 0,
368 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
369 CLOCK_GATING_DISABLE);
370 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
371
372 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
373 audio->inst, value);
374 }
375
dce_aud_az_disable(struct audio * audio)376 void dce_aud_az_disable(struct audio *audio)
377 {
378 uint32_t value;
379 DC_LOGGER_INIT();
380
381 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
382 set_reg_field_value(value, 1,
383 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
384 CLOCK_GATING_DISABLE);
385 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
386
387 set_reg_field_value(value, 0,
388 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
389 AUDIO_ENABLED);
390 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
391
392 set_reg_field_value(value, 0,
393 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
394 CLOCK_GATING_DISABLE);
395 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
396 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
397 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
398 audio->inst, value);
399 }
400
dce_aud_az_configure(struct audio * audio,enum signal_type signal,const struct audio_crtc_info * crtc_info,const struct audio_info * audio_info)401 void dce_aud_az_configure(
402 struct audio *audio,
403 enum signal_type signal,
404 const struct audio_crtc_info *crtc_info,
405 const struct audio_info *audio_info)
406 {
407 struct dce_audio *aud = DCE_AUD(audio);
408
409 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
410 uint32_t value;
411 uint32_t field = 0;
412 enum audio_format_code audio_format_code;
413 uint32_t format_index;
414 uint32_t index;
415 bool is_ac3_supported = false;
416 union audio_sample_rates sample_rate;
417 uint32_t strlen = 0;
418 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
419 set_reg_field_value(value, 1,
420 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
421 CLOCK_GATING_DISABLE);
422 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
423
424 /* Speaker Allocation */
425 /*
426 uint32_t value;
427 uint32_t field = 0;*/
428 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
429
430 set_reg_field_value(value,
431 speakers,
432 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
433 SPEAKER_ALLOCATION);
434
435 /* LFE_PLAYBACK_LEVEL = LFEPBL
436 * LFEPBL = 0 : Unknown or refer to other information
437 * LFEPBL = 1 : 0dB playback
438 * LFEPBL = 2 : +10dB playback
439 * LFE_BL = 3 : Reserved
440 */
441 set_reg_field_value(value,
442 0,
443 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
444 LFE_PLAYBACK_LEVEL);
445 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
446 * why are we writing to it? DCE8 does not write this */
447
448
449 set_reg_field_value(value,
450 0,
451 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
452 HDMI_CONNECTION);
453
454 set_reg_field_value(value,
455 0,
456 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
457 DP_CONNECTION);
458
459 field = get_reg_field_value(value,
460 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
461 EXTRA_CONNECTION_INFO);
462
463 field &= ~0x1;
464
465 set_reg_field_value(value,
466 field,
467 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
468 EXTRA_CONNECTION_INFO);
469
470 /* set audio for output signal */
471 switch (signal) {
472 case SIGNAL_TYPE_HDMI_TYPE_A:
473 set_reg_field_value(value,
474 1,
475 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
476 HDMI_CONNECTION);
477
478 break;
479
480 case SIGNAL_TYPE_EDP:
481 case SIGNAL_TYPE_DISPLAY_PORT:
482 case SIGNAL_TYPE_DISPLAY_PORT_MST:
483 set_reg_field_value(value,
484 1,
485 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
486 DP_CONNECTION);
487 break;
488 default:
489 BREAK_TO_DEBUGGER();
490 break;
491 }
492
493 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
494
495 /* Audio Descriptors */
496 /* pass through all formats */
497 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
498 format_index++) {
499 audio_format_code =
500 (AUDIO_FORMAT_CODE_FIRST + format_index);
501
502 /* those are unsupported, skip programming */
503 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
504 audio_format_code == AUDIO_FORMAT_CODE_DST)
505 continue;
506
507 value = 0;
508
509 /* check if supported */
510 if (is_audio_format_supported(
511 audio_info, audio_format_code, &index)) {
512 const struct audio_mode *audio_mode =
513 &audio_info->modes[index];
514 union audio_sample_rates sample_rates =
515 audio_mode->sample_rates;
516 uint8_t byte2 = audio_mode->max_bit_rate;
517 uint8_t channel_count = audio_mode->channel_count;
518
519 /* adjust specific properties */
520 switch (audio_format_code) {
521 case AUDIO_FORMAT_CODE_LINEARPCM: {
522
523 check_audio_bandwidth(
524 crtc_info,
525 channel_count,
526 signal,
527 &sample_rates);
528
529 byte2 = audio_mode->sample_size;
530
531 set_reg_field_value(value,
532 sample_rates.all,
533 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
534 SUPPORTED_FREQUENCIES_STEREO);
535 }
536 break;
537 case AUDIO_FORMAT_CODE_AC3:
538 is_ac3_supported = true;
539 break;
540 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
541 case AUDIO_FORMAT_CODE_DTS_HD:
542 case AUDIO_FORMAT_CODE_MAT_MLP:
543 case AUDIO_FORMAT_CODE_DST:
544 case AUDIO_FORMAT_CODE_WMAPRO:
545 byte2 = audio_mode->vendor_specific;
546 break;
547 default:
548 break;
549 }
550
551 /* fill audio format data */
552 set_reg_field_value(value,
553 channel_count - 1,
554 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
555 MAX_CHANNELS);
556
557 set_reg_field_value(value,
558 sample_rates.all,
559 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
560 SUPPORTED_FREQUENCIES);
561
562 set_reg_field_value(value,
563 byte2,
564 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
565 DESCRIPTOR_BYTE_2);
566 } /* if */
567
568 AZ_REG_WRITE(
569 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
570 value);
571 } /* for */
572
573 if (is_ac3_supported)
574 /* todo: this reg global. why program global register? */
575 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
576 0x05);
577
578 /* check for 192khz/8-Ch support for HBR requirements */
579 sample_rate.all = 0;
580 sample_rate.rate.RATE_192 = 1;
581
582 check_audio_bandwidth(
583 crtc_info,
584 8,
585 signal,
586 &sample_rate);
587
588 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
589
590 /* Audio and Video Lipsync */
591 set_video_latency(audio, audio_info->video_latency);
592 set_audio_latency(audio, audio_info->audio_latency);
593
594 value = 0;
595 set_reg_field_value(value, audio_info->manufacture_id,
596 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
597 MANUFACTURER_ID);
598
599 set_reg_field_value(value, audio_info->product_id,
600 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
601 PRODUCT_ID);
602
603 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
604 value);
605
606 value = 0;
607
608 /*get display name string length */
609 while (audio_info->display_name[strlen++] != '\0') {
610 if (strlen >=
611 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
612 break;
613 }
614 set_reg_field_value(value, strlen,
615 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
616 SINK_DESCRIPTION_LEN);
617
618 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
619 value);
620 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
621 audio->inst, value, audio_info->display_name);
622
623 /*
624 *write the port ID:
625 *PORT_ID0 = display index
626 *PORT_ID1 = 16bit BDF
627 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
628 */
629
630 value = 0;
631
632 set_reg_field_value(value, audio_info->port_id[0],
633 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
634 PORT_ID0);
635
636 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
637
638 value = 0;
639 set_reg_field_value(value, audio_info->port_id[1],
640 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
641 PORT_ID1);
642
643 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
644
645 /*write the 18 char monitor string */
646
647 value = 0;
648 set_reg_field_value(value, audio_info->display_name[0],
649 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
650 DESCRIPTION0);
651
652 set_reg_field_value(value, audio_info->display_name[1],
653 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
654 DESCRIPTION1);
655
656 set_reg_field_value(value, audio_info->display_name[2],
657 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
658 DESCRIPTION2);
659
660 set_reg_field_value(value, audio_info->display_name[3],
661 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
662 DESCRIPTION3);
663
664 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
665
666 value = 0;
667 set_reg_field_value(value, audio_info->display_name[4],
668 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
669 DESCRIPTION4);
670
671 set_reg_field_value(value, audio_info->display_name[5],
672 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
673 DESCRIPTION5);
674
675 set_reg_field_value(value, audio_info->display_name[6],
676 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
677 DESCRIPTION6);
678
679 set_reg_field_value(value, audio_info->display_name[7],
680 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
681 DESCRIPTION7);
682
683 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
684
685 value = 0;
686 set_reg_field_value(value, audio_info->display_name[8],
687 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
688 DESCRIPTION8);
689
690 set_reg_field_value(value, audio_info->display_name[9],
691 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
692 DESCRIPTION9);
693
694 set_reg_field_value(value, audio_info->display_name[10],
695 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
696 DESCRIPTION10);
697
698 set_reg_field_value(value, audio_info->display_name[11],
699 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
700 DESCRIPTION11);
701
702 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
703
704 value = 0;
705 set_reg_field_value(value, audio_info->display_name[12],
706 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
707 DESCRIPTION12);
708
709 set_reg_field_value(value, audio_info->display_name[13],
710 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
711 DESCRIPTION13);
712
713 set_reg_field_value(value, audio_info->display_name[14],
714 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
715 DESCRIPTION14);
716
717 set_reg_field_value(value, audio_info->display_name[15],
718 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
719 DESCRIPTION15);
720
721 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
722
723 value = 0;
724 set_reg_field_value(value, audio_info->display_name[16],
725 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
726 DESCRIPTION16);
727
728 set_reg_field_value(value, audio_info->display_name[17],
729 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
730 DESCRIPTION17);
731
732 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
733 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
734 set_reg_field_value(value, 0,
735 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
736 CLOCK_GATING_DISABLE);
737 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
738 }
739
740 /*
741 * todo: wall clk related functionality probably belong to clock_src.
742 */
743
744 /* search pixel clock value for Azalia HDMI Audio */
get_azalia_clock_info_hdmi(uint32_t crtc_pixel_clock_100hz,uint32_t actual_pixel_clock_100Hz,struct azalia_clock_info * azalia_clock_info)745 static void get_azalia_clock_info_hdmi(
746 uint32_t crtc_pixel_clock_100hz,
747 uint32_t actual_pixel_clock_100Hz,
748 struct azalia_clock_info *azalia_clock_info)
749 {
750 /* audio_dto_phase= 24 * 10,000;
751 * 24MHz in [100Hz] units */
752 azalia_clock_info->audio_dto_phase =
753 24 * 10000;
754
755 /* audio_dto_module = PCLKFrequency * 10,000;
756 * [khz] -> [100Hz] */
757 azalia_clock_info->audio_dto_module =
758 actual_pixel_clock_100Hz;
759 }
760
get_azalia_clock_info_dp(uint32_t requested_pixel_clock_100Hz,const struct audio_pll_info * pll_info,struct azalia_clock_info * azalia_clock_info)761 static void get_azalia_clock_info_dp(
762 uint32_t requested_pixel_clock_100Hz,
763 const struct audio_pll_info *pll_info,
764 struct azalia_clock_info *azalia_clock_info)
765 {
766 /* Reported dpDtoSourceClockInkhz value for
767 * DCE8 already adjusted for SS, do not need any
768 * adjustment here anymore
769 */
770
771 /*audio_dto_phase = 24 * 10,000;
772 * 24MHz in [100Hz] units */
773 azalia_clock_info->audio_dto_phase = 24 * 10000;
774
775 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
776 * [khz] ->[100Hz] */
777 azalia_clock_info->audio_dto_module =
778 pll_info->dp_dto_source_clock_in_khz * 10;
779 }
780
dce_aud_wall_dto_setup(struct audio * audio,enum signal_type signal,const struct audio_crtc_info * crtc_info,const struct audio_pll_info * pll_info)781 void dce_aud_wall_dto_setup(
782 struct audio *audio,
783 enum signal_type signal,
784 const struct audio_crtc_info *crtc_info,
785 const struct audio_pll_info *pll_info)
786 {
787 struct dce_audio *aud = DCE_AUD(audio);
788
789 struct azalia_clock_info clock_info = { 0 };
790
791 if (dc_is_hdmi_tmds_signal(signal)) {
792 uint32_t src_sel;
793
794 /*DTO0 Programming goal:
795 -generate 24MHz, 128*Fs from 24MHz
796 -use DTO0 when an active HDMI port is connected
797 (optionally a DP is connected) */
798
799 /* calculate DTO settings */
800 get_azalia_clock_info_hdmi(
801 crtc_info->requested_pixel_clock_100Hz,
802 crtc_info->calculated_pixel_clock_100Hz,
803 &clock_info);
804
805 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
806 "calculated_pixel_clock_100Hz =%d\n"\
807 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
808 crtc_info->requested_pixel_clock_100Hz,\
809 crtc_info->calculated_pixel_clock_100Hz,\
810 clock_info.audio_dto_module,\
811 clock_info.audio_dto_phase);
812
813 /* On TN/SI, Program DTO source select and DTO select before
814 programming DTO modulo and DTO phase. These bits must be
815 programmed first, otherwise there will be no HDMI audio at boot
816 up. This is a HW sequence change (different from old ASICs).
817 Caution when changing this programming sequence.
818
819 HDMI enabled, using DTO0
820 program master CRTC for DTO0 */
821 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
822 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
823 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
824 DCCG_AUDIO_DTO_SEL, 0);
825
826 /* module */
827 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
828 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
829
830 /* phase */
831 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
832 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
833 } else {
834 /*DTO1 Programming goal:
835 -generate 24MHz, 512*Fs, 128*Fs from 24MHz
836 -default is to used DTO1, and switch to DTO0 when an audio
837 master HDMI port is connected
838 -use as default for DP
839
840 calculate DTO settings */
841 get_azalia_clock_info_dp(
842 crtc_info->requested_pixel_clock_100Hz,
843 pll_info,
844 &clock_info);
845
846 /* Program DTO select before programming DTO modulo and DTO
847 phase. default to use DTO1 */
848
849 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
850 DCCG_AUDIO_DTO_SEL, 1);
851
852 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
853 * Select 512fs for DP TODO: web register definition
854 * does not match register header file
855 * DCE11 version it's commented out while DCE8 it's set to 1
856 */
857
858 /* module */
859 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
860 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
861
862 /* phase */
863 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
864 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
865
866 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
867 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
868
869 }
870 }
871
872 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_aud_wall_dto_setup(struct audio * audio,enum signal_type signal,const struct audio_crtc_info * crtc_info,const struct audio_pll_info * pll_info)873 static void dce60_aud_wall_dto_setup(
874 struct audio *audio,
875 enum signal_type signal,
876 const struct audio_crtc_info *crtc_info,
877 const struct audio_pll_info *pll_info)
878 {
879 struct dce_audio *aud = DCE_AUD(audio);
880
881 struct azalia_clock_info clock_info = { 0 };
882
883 if (dc_is_hdmi_signal(signal)) {
884 uint32_t src_sel;
885
886 /*DTO0 Programming goal:
887 -generate 24MHz, 128*Fs from 24MHz
888 -use DTO0 when an active HDMI port is connected
889 (optionally a DP is connected) */
890
891 /* calculate DTO settings */
892 get_azalia_clock_info_hdmi(
893 crtc_info->requested_pixel_clock_100Hz,
894 crtc_info->calculated_pixel_clock_100Hz,
895 &clock_info);
896
897 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
898 "calculated_pixel_clock_100Hz =%d\n"\
899 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
900 crtc_info->requested_pixel_clock_100Hz,\
901 crtc_info->calculated_pixel_clock_100Hz,\
902 clock_info.audio_dto_module,\
903 clock_info.audio_dto_phase);
904
905 /* On TN/SI, Program DTO source select and DTO select before
906 programming DTO modulo and DTO phase. These bits must be
907 programmed first, otherwise there will be no HDMI audio at boot
908 up. This is a HW sequence change (different from old ASICs).
909 Caution when changing this programming sequence.
910
911 HDMI enabled, using DTO0
912 program master CRTC for DTO0 */
913 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
914 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
915 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
916 DCCG_AUDIO_DTO_SEL, 0);
917
918 /* module */
919 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
920 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
921
922 /* phase */
923 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
924 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
925 } else {
926 /*DTO1 Programming goal:
927 -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs)
928 -default is to used DTO1, and switch to DTO0 when an audio
929 master HDMI port is connected
930 -use as default for DP
931
932 calculate DTO settings */
933 get_azalia_clock_info_dp(
934 crtc_info->requested_pixel_clock_100Hz,
935 pll_info,
936 &clock_info);
937
938 /* Program DTO select before programming DTO modulo and DTO
939 phase. default to use DTO1 */
940
941 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
942 DCCG_AUDIO_DTO_SEL, 1);
943
944 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
945 * Cannot select 512fs for DP
946 *
947 * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
948 */
949
950 /* module */
951 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
952 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
953
954 /* phase */
955 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
956 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
957
958 /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */
959
960 }
961 }
962 #endif
963
dce_aud_endpoint_valid(struct audio * audio)964 static bool dce_aud_endpoint_valid(struct audio *audio)
965 {
966 uint32_t value;
967 uint32_t port_connectivity;
968
969 value = AZ_REG_READ(
970 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
971
972 port_connectivity = get_reg_field_value(value,
973 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
974 PORT_CONNECTIVITY);
975
976 return !(port_connectivity == 1);
977 }
978
979 /* initialize HW state */
dce_aud_hw_init(struct audio * audio)980 void dce_aud_hw_init(
981 struct audio *audio)
982 {
983 uint32_t value;
984 struct dce_audio *aud = DCE_AUD(audio);
985
986 /* we only need to program the following registers once, so we only do
987 it for the inst 0*/
988 if (audio->inst != 0)
989 return;
990
991 /* Suport R5 - 32khz
992 * Suport R6 - 44.1khz
993 * Suport R7 - 48khz
994 */
995 /*disable clock gating before write to endpoint register*/
996 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
997 set_reg_field_value(value, 1,
998 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
999 CLOCK_GATING_DISABLE);
1000 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1001 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
1002 AUDIO_RATE_CAPABILITIES, 0x70);
1003
1004 /*Keep alive bit to verify HW block in BU. */
1005 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
1006 CLKSTOP, 1,
1007 EPSS, 1);
1008 set_reg_field_value(value, 0,
1009 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1010 CLOCK_GATING_DISABLE);
1011 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1012 }
1013
1014 static const struct audio_funcs funcs = {
1015 .endpoint_valid = dce_aud_endpoint_valid,
1016 .hw_init = dce_aud_hw_init,
1017 .wall_dto_setup = dce_aud_wall_dto_setup,
1018 .az_enable = dce_aud_az_enable,
1019 .az_disable = dce_aud_az_disable,
1020 .az_configure = dce_aud_az_configure,
1021 .destroy = dce_aud_destroy,
1022 };
1023
1024 #if defined(CONFIG_DRM_AMD_DC_SI)
1025 static const struct audio_funcs dce60_funcs = {
1026 .endpoint_valid = dce_aud_endpoint_valid,
1027 .hw_init = dce_aud_hw_init,
1028 .wall_dto_setup = dce60_aud_wall_dto_setup,
1029 .az_enable = dce_aud_az_enable,
1030 .az_disable = dce_aud_az_disable,
1031 .az_configure = dce_aud_az_configure,
1032 .destroy = dce_aud_destroy,
1033 };
1034 #endif
1035
dce_aud_destroy(struct audio ** audio)1036 void dce_aud_destroy(struct audio **audio)
1037 {
1038 struct dce_audio *aud = DCE_AUD(*audio);
1039
1040 kfree(aud);
1041 *audio = NULL;
1042 }
1043
dce_audio_create(struct dc_context * ctx,unsigned int inst,const struct dce_audio_registers * reg,const struct dce_audio_shift * shifts,const struct dce_audio_mask * masks)1044 struct audio *dce_audio_create(
1045 struct dc_context *ctx,
1046 unsigned int inst,
1047 const struct dce_audio_registers *reg,
1048 const struct dce_audio_shift *shifts,
1049 const struct dce_audio_mask *masks
1050 )
1051 {
1052 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
1053
1054 if (audio == NULL) {
1055 ASSERT_CRITICAL(audio);
1056 return NULL;
1057 }
1058
1059 audio->base.ctx = ctx;
1060 audio->base.inst = inst;
1061 audio->base.funcs = &funcs;
1062
1063 audio->regs = reg;
1064 audio->shifts = shifts;
1065 audio->masks = masks;
1066 return &audio->base;
1067 }
1068
1069 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_audio_create(struct dc_context * ctx,unsigned int inst,const struct dce_audio_registers * reg,const struct dce_audio_shift * shifts,const struct dce_audio_mask * masks)1070 struct audio *dce60_audio_create(
1071 struct dc_context *ctx,
1072 unsigned int inst,
1073 const struct dce_audio_registers *reg,
1074 const struct dce_audio_shift *shifts,
1075 const struct dce_audio_mask *masks
1076 )
1077 {
1078 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
1079
1080 if (audio == NULL) {
1081 ASSERT_CRITICAL(audio);
1082 return NULL;
1083 }
1084
1085 audio->base.ctx = ctx;
1086 audio->base.inst = inst;
1087 audio->base.funcs = &dce60_funcs;
1088
1089 audio->regs = reg;
1090 audio->shifts = shifts;
1091 audio->masks = masks;
1092 return &audio->base;
1093 }
1094 #endif
1095