1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "core_types.h"
29
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33
34
35 #define NUM_PHASES 64
36 #define HORZ_MAX_TAPS 8
37 #define VERT_MAX_TAPS 8
38
39 #define BLACK_OFFSET_RGB_Y 0x0
40 #define BLACK_OFFSET_CBCR 0x8000
41
42 #define REG(reg)\
43 dpp->tf_regs->reg
44
45 #define CTX \
46 dpp->base.ctx
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51
52 enum dcn10_coef_filter_type_sel {
53 SCL_COEF_LUMA_VERT_FILTER = 0,
54 SCL_COEF_LUMA_HORZ_FILTER = 1,
55 SCL_COEF_CHROMA_VERT_FILTER = 2,
56 SCL_COEF_CHROMA_HORZ_FILTER = 3,
57 SCL_COEF_ALPHA_VERT_FILTER = 4,
58 SCL_COEF_ALPHA_HORZ_FILTER = 5
59 };
60
61 enum dscl_autocal_mode {
62 AUTOCAL_MODE_OFF = 0,
63
64 /* Autocal calculate the scaling ratio and initial phase and the
65 * DSCL_MODE_SEL must be set to 1
66 */
67 AUTOCAL_MODE_AUTOSCALE = 1,
68 /* Autocal perform auto centering without replication and the
69 * DSCL_MODE_SEL must be set to 0
70 */
71 AUTOCAL_MODE_AUTOCENTER = 2,
72 /* Autocal perform auto centering and auto replication and the
73 * DSCL_MODE_SEL must be set to 0
74 */
75 AUTOCAL_MODE_AUTOREPLICATE = 3
76 };
77
78 enum dscl_mode_sel {
79 DSCL_MODE_SCALING_444_BYPASS = 0,
80 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
81 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
82 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
83 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
84 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
85 DSCL_MODE_DSCL_BYPASS = 6
86 };
87
dpp1_dscl_set_overscan(struct dcn10_dpp * dpp,const struct scaler_data * data)88 static void dpp1_dscl_set_overscan(
89 struct dcn10_dpp *dpp,
90 const struct scaler_data *data)
91 {
92 uint32_t left = data->recout.x;
93 uint32_t top = data->recout.y;
94
95 int right = data->h_active - data->recout.x - data->recout.width;
96 int bottom = data->v_active - data->recout.y - data->recout.height;
97
98 if (right < 0) {
99 BREAK_TO_DEBUGGER();
100 right = 0;
101 }
102 if (bottom < 0) {
103 BREAK_TO_DEBUGGER();
104 bottom = 0;
105 }
106
107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
108 EXT_OVERSCAN_LEFT, left,
109 EXT_OVERSCAN_RIGHT, right);
110
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
112 EXT_OVERSCAN_BOTTOM, bottom,
113 EXT_OVERSCAN_TOP, top);
114 }
115
dpp1_dscl_set_otg_blank(struct dcn10_dpp * dpp,const struct scaler_data * data)116 static void dpp1_dscl_set_otg_blank(
117 struct dcn10_dpp *dpp, const struct scaler_data *data)
118 {
119 uint32_t h_blank_start = data->h_active;
120 uint32_t h_blank_end = 0;
121 uint32_t v_blank_start = data->v_active;
122 uint32_t v_blank_end = 0;
123
124 REG_SET_2(OTG_H_BLANK, 0,
125 OTG_H_BLANK_START, h_blank_start,
126 OTG_H_BLANK_END, h_blank_end);
127
128 REG_SET_2(OTG_V_BLANK, 0,
129 OTG_V_BLANK_START, v_blank_start,
130 OTG_V_BLANK_END, v_blank_end);
131 }
132
dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)133 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
134 {
135 if (depth == LB_PIXEL_DEPTH_30BPP)
136 return 0; /* 10 bpc */
137 else if (depth == LB_PIXEL_DEPTH_24BPP)
138 return 1; /* 8 bpc */
139 else if (depth == LB_PIXEL_DEPTH_18BPP)
140 return 2; /* 6 bpc */
141 else if (depth == LB_PIXEL_DEPTH_36BPP)
142 return 3; /* 12 bpc */
143 else {
144 ASSERT(0);
145 return -1; /* Unsupported */
146 }
147 }
148
dpp1_dscl_is_video_format(enum pixel_format format)149 static bool dpp1_dscl_is_video_format(enum pixel_format format)
150 {
151 if (format >= PIXEL_FORMAT_VIDEO_BEGIN
152 && format <= PIXEL_FORMAT_VIDEO_END)
153 return true;
154 else
155 return false;
156 }
157
dpp1_dscl_is_420_format(enum pixel_format format)158 static bool dpp1_dscl_is_420_format(enum pixel_format format)
159 {
160 if (format == PIXEL_FORMAT_420BPP8 ||
161 format == PIXEL_FORMAT_420BPP10)
162 return true;
163 else
164 return false;
165 }
166
dpp1_dscl_get_dscl_mode(struct dpp * dpp_base,const struct scaler_data * data,bool dbg_always_scale)167 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
168 struct dpp *dpp_base,
169 const struct scaler_data *data,
170 bool dbg_always_scale)
171 {
172 const long long one = dc_fixpt_one.value;
173
174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
175 /* DSCL is processing data in fixed format */
176 if (data->format == PIXEL_FORMAT_FP16)
177 return DSCL_MODE_DSCL_BYPASS;
178 }
179
180 if (data->ratios.horz.value == one
181 && data->ratios.vert.value == one
182 && data->ratios.horz_c.value == one
183 && data->ratios.vert_c.value == one
184 && !dbg_always_scale)
185 return DSCL_MODE_SCALING_444_BYPASS;
186
187 if (!dpp1_dscl_is_420_format(data->format)) {
188 if (dpp1_dscl_is_video_format(data->format))
189 return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
190 else
191 return DSCL_MODE_SCALING_444_RGB_ENABLE;
192 }
193 if (data->ratios.horz.value == one && data->ratios.vert.value == one)
194 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
195 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
196 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
197
198 return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
199 }
200
dpp1_power_on_dscl(struct dpp * dpp_base,bool power_on)201 static void dpp1_power_on_dscl(
202 struct dpp *dpp_base,
203 bool power_on)
204 {
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
206
207 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {
208 if (power_on) {
209 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0);
210 REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);
211 } else {
212 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {
213 dpp->base.ctx->dc->optimized_required = true;
214 dpp->base.deferred_reg_writes.bits.disable_dscl = true;
215 } else {
216 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
217 }
218 }
219 }
220 }
221
222
dpp1_dscl_set_lb(struct dcn10_dpp * dpp,const struct line_buffer_params * lb_params,enum lb_memory_config mem_size_config)223 static void dpp1_dscl_set_lb(
224 struct dcn10_dpp *dpp,
225 const struct line_buffer_params *lb_params,
226 enum lb_memory_config mem_size_config)
227 {
228 uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */
229
230 /* LB */
231 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
232 /* DSCL caps: pixel data processed in fixed format */
233 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
234 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
235
236 REG_SET_7(LB_DATA_FORMAT, 0,
237 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
238 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
239 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
240 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
241 DITHER_EN, 0, /* Dithering enable: Disabled */
242 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
243 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
244 }
245 else {
246 /* DSCL caps: pixel data processed in float format */
247 REG_SET_2(LB_DATA_FORMAT, 0,
248 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
249 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
250 }
251
252 if (dpp->base.caps->max_lb_partitions == 31)
253 max_partitions = 31;
254
255 REG_SET_2(LB_MEMORY_CTRL, 0,
256 MEMORY_CONFIG, mem_size_config,
257 LB_MAX_PARTITIONS, max_partitions);
258 }
259
dpp1_dscl_get_filter_coeffs_64p(int taps,struct fixed31_32 ratio)260 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
261 {
262 if (taps == 8)
263 return get_filter_8tap_64p(ratio);
264 else if (taps == 7)
265 return get_filter_7tap_64p(ratio);
266 else if (taps == 6)
267 return get_filter_6tap_64p(ratio);
268 else if (taps == 5)
269 return get_filter_5tap_64p(ratio);
270 else if (taps == 4)
271 return get_filter_4tap_64p(ratio);
272 else if (taps == 3)
273 return get_filter_3tap_64p(ratio);
274 else if (taps == 2)
275 return get_filter_2tap_64p();
276 else if (taps == 1)
277 return NULL;
278 else {
279 /* should never happen, bug */
280 BREAK_TO_DEBUGGER();
281 return NULL;
282 }
283 }
284
dpp1_dscl_set_scaler_filter(struct dcn10_dpp * dpp,uint32_t taps,enum dcn10_coef_filter_type_sel filter_type,const uint16_t * filter)285 static void dpp1_dscl_set_scaler_filter(
286 struct dcn10_dpp *dpp,
287 uint32_t taps,
288 enum dcn10_coef_filter_type_sel filter_type,
289 const uint16_t *filter)
290 {
291 const int tap_pairs = (taps + 1) / 2;
292 int phase;
293 int pair;
294 uint16_t odd_coef, even_coef;
295
296 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
297 SCL_COEF_RAM_TAP_PAIR_IDX, 0,
298 SCL_COEF_RAM_PHASE, 0,
299 SCL_COEF_RAM_FILTER_TYPE, filter_type);
300
301 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
302 for (pair = 0; pair < tap_pairs; pair++) {
303 even_coef = filter[phase * taps + 2 * pair];
304 if ((pair * 2 + 1) < taps)
305 odd_coef = filter[phase * taps + 2 * pair + 1];
306 else
307 odd_coef = 0;
308
309 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
310 /* Even tap coefficient (bits 1:0 fixed to 0) */
311 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
312 /* Write/read control for even coefficient */
313 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
314 /* Odd tap coefficient (bits 1:0 fixed to 0) */
315 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
316 /* Write/read control for odd coefficient */
317 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
318 }
319 }
320
321 }
322
dpp1_dscl_set_scl_filter(struct dcn10_dpp * dpp,const struct scaler_data * scl_data,bool chroma_coef_mode)323 static void dpp1_dscl_set_scl_filter(
324 struct dcn10_dpp *dpp,
325 const struct scaler_data *scl_data,
326 bool chroma_coef_mode)
327 {
328 bool h_2tap_hardcode_coef_en = false;
329 bool v_2tap_hardcode_coef_en = false;
330 bool h_2tap_sharp_en = false;
331 bool v_2tap_sharp_en = false;
332 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
333 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
334 bool coef_ram_current;
335 const uint16_t *filter_h = NULL;
336 const uint16_t *filter_v = NULL;
337 const uint16_t *filter_h_c = NULL;
338 const uint16_t *filter_v_c = NULL;
339
340 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
341 && scl_data->taps.h_taps_c < 3
342 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
343 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
344 && scl_data->taps.v_taps_c < 3
345 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
346
347 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
348 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
349
350 REG_UPDATE_6(DSCL_2TAP_CONTROL,
351 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
352 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
353 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
354 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
355 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
356 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
357
358 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
359 bool filter_updated = false;
360
361 filter_h = dpp1_dscl_get_filter_coeffs_64p(
362 scl_data->taps.h_taps, scl_data->ratios.horz);
363 filter_v = dpp1_dscl_get_filter_coeffs_64p(
364 scl_data->taps.v_taps, scl_data->ratios.vert);
365
366 filter_updated = (filter_h && (filter_h != dpp->filter_h))
367 || (filter_v && (filter_v != dpp->filter_v));
368
369 if (chroma_coef_mode) {
370 filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
371 scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
372 filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
373 scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
374 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
375 || (filter_v_c && (filter_v_c != dpp->filter_v_c));
376 }
377
378 if (filter_updated) {
379 uint32_t scl_mode = REG_READ(SCL_MODE);
380
381 if (!h_2tap_hardcode_coef_en && filter_h) {
382 dpp1_dscl_set_scaler_filter(
383 dpp, scl_data->taps.h_taps,
384 SCL_COEF_LUMA_HORZ_FILTER, filter_h);
385 }
386 dpp->filter_h = filter_h;
387 if (!v_2tap_hardcode_coef_en && filter_v) {
388 dpp1_dscl_set_scaler_filter(
389 dpp, scl_data->taps.v_taps,
390 SCL_COEF_LUMA_VERT_FILTER, filter_v);
391 }
392 dpp->filter_v = filter_v;
393 if (chroma_coef_mode) {
394 if (!h_2tap_hardcode_coef_en && filter_h_c) {
395 dpp1_dscl_set_scaler_filter(
396 dpp, scl_data->taps.h_taps_c,
397 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
398 }
399 if (!v_2tap_hardcode_coef_en && filter_v_c) {
400 dpp1_dscl_set_scaler_filter(
401 dpp, scl_data->taps.v_taps_c,
402 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
403 }
404 }
405 dpp->filter_h_c = filter_h_c;
406 dpp->filter_v_c = filter_v_c;
407
408 coef_ram_current = get_reg_field_value_ex(
409 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
410 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
411
412 /* Swap coefficient RAM and set chroma coefficient mode */
413 REG_SET_2(SCL_MODE, scl_mode,
414 SCL_COEF_RAM_SELECT, !coef_ram_current,
415 SCL_CHROMA_COEF_MODE, chroma_coef_mode);
416 }
417 }
418 }
419
dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)420 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
421 {
422 if (depth == LB_PIXEL_DEPTH_30BPP)
423 return 10;
424 else if (depth == LB_PIXEL_DEPTH_24BPP)
425 return 8;
426 else if (depth == LB_PIXEL_DEPTH_18BPP)
427 return 6;
428 else if (depth == LB_PIXEL_DEPTH_36BPP)
429 return 12;
430 else {
431 BREAK_TO_DEBUGGER();
432 return -1; /* Unsupported */
433 }
434 }
435
dpp1_dscl_calc_lb_num_partitions(const struct scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c)436 void dpp1_dscl_calc_lb_num_partitions(
437 const struct scaler_data *scl_data,
438 enum lb_memory_config lb_config,
439 int *num_part_y,
440 int *num_part_c)
441 {
442 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,
443 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
444
445 int line_size = scl_data->viewport.width < scl_data->recout.width ?
446 scl_data->viewport.width : scl_data->recout.width;
447 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
448 scl_data->viewport_c.width : scl_data->recout.width;
449
450 if (line_size == 0)
451 line_size = 1;
452
453 if (line_size_c == 0)
454 line_size_c = 1;
455
456
457 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
458 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
459 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
460 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
461
462 if (lb_config == LB_MEMORY_CONFIG_1) {
463 lb_memory_size = 816;
464 lb_memory_size_c = 816;
465 lb_memory_size_a = 984;
466 } else if (lb_config == LB_MEMORY_CONFIG_2) {
467 lb_memory_size = 1088;
468 lb_memory_size_c = 1088;
469 lb_memory_size_a = 1312;
470 } else if (lb_config == LB_MEMORY_CONFIG_3) {
471 /* 420 mode: using 3rd mem from Y, Cr and Cb */
472 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
473 lb_memory_size_c = 816 + 1088;
474 lb_memory_size_a = 984 + 1312 + 456;
475 } else {
476 lb_memory_size = 816 + 1088 + 848;
477 lb_memory_size_c = 816 + 1088 + 848;
478 lb_memory_size_a = 984 + 1312 + 456;
479 }
480 *num_part_y = lb_memory_size / memory_line_size_y;
481 *num_part_c = lb_memory_size_c / memory_line_size_c;
482 num_partitions_a = lb_memory_size_a / memory_line_size_a;
483
484 if (scl_data->lb_params.alpha_en
485 && (num_partitions_a < *num_part_y))
486 *num_part_y = num_partitions_a;
487
488 if (*num_part_y > 64)
489 *num_part_y = 64;
490 if (*num_part_c > 64)
491 *num_part_c = 64;
492
493 }
494
dpp1_dscl_is_lb_conf_valid(int ceil_vratio,int num_partitions,int vtaps)495 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
496 {
497 if (ceil_vratio > 2)
498 return vtaps <= (num_partitions - ceil_vratio + 2);
499 else
500 return vtaps <= num_partitions;
501 }
502
503 /*find first match configuration which meets the min required lb size*/
dpp1_dscl_find_lb_memory_config(struct dcn10_dpp * dpp,const struct scaler_data * scl_data)504 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
505 const struct scaler_data *scl_data)
506 {
507 int num_part_y, num_part_c;
508 int vtaps = scl_data->taps.v_taps;
509 int vtaps_c = scl_data->taps.v_taps_c;
510 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
511 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
512
513 if (dpp->base.ctx->dc->debug.use_max_lb) {
514 if (scl_data->format == PIXEL_FORMAT_420BPP8
515 || scl_data->format == PIXEL_FORMAT_420BPP10)
516 return LB_MEMORY_CONFIG_3;
517 return LB_MEMORY_CONFIG_0;
518 }
519
520 dpp->base.caps->dscl_calc_lb_num_partitions(
521 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
522
523 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
524 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
525 return LB_MEMORY_CONFIG_1;
526
527 dpp->base.caps->dscl_calc_lb_num_partitions(
528 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
529
530 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
531 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
532 return LB_MEMORY_CONFIG_2;
533
534 if (scl_data->format == PIXEL_FORMAT_420BPP8
535 || scl_data->format == PIXEL_FORMAT_420BPP10) {
536 dpp->base.caps->dscl_calc_lb_num_partitions(
537 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
538
539 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
540 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
541 return LB_MEMORY_CONFIG_3;
542 }
543
544 dpp->base.caps->dscl_calc_lb_num_partitions(
545 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
546
547 /*Ensure we can support the requested number of vtaps*/
548 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
549 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
550
551 return LB_MEMORY_CONFIG_0;
552 }
553
dpp1_dscl_set_scaler_auto_scale(struct dpp * dpp_base,const struct scaler_data * scl_data)554 void dpp1_dscl_set_scaler_auto_scale(
555 struct dpp *dpp_base,
556 const struct scaler_data *scl_data)
557 {
558 enum lb_memory_config lb_config;
559 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
560 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
561 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
562 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
563 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
564
565 dpp1_dscl_set_overscan(dpp, scl_data);
566
567 dpp1_dscl_set_otg_blank(dpp, scl_data);
568
569 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
570
571 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
572 return;
573
574 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
575 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
576
577 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
578 return;
579
580 /* TODO: v_min */
581 REG_SET_3(DSCL_AUTOCAL, 0,
582 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
583 AUTOCAL_NUM_PIPE, 0,
584 AUTOCAL_PIPE_ID, 0);
585
586 /* Black offsets */
587 if (ycbcr)
588 REG_SET_2(SCL_BLACK_OFFSET, 0,
589 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
590 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
591 else
592
593 REG_SET_2(SCL_BLACK_OFFSET, 0,
594 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
595 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
596
597 REG_SET_4(SCL_TAP_CONTROL, 0,
598 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
599 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
600 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
601 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
602
603 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
604 }
605
606
dpp1_dscl_set_manual_ratio_init(struct dcn10_dpp * dpp,const struct scaler_data * data)607 static void dpp1_dscl_set_manual_ratio_init(
608 struct dcn10_dpp *dpp, const struct scaler_data *data)
609 {
610 uint32_t init_frac = 0;
611 uint32_t init_int = 0;
612
613 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
614 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5);
615
616 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
617 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5);
618
619 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
620 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5);
621
622 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
623 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5);
624
625 /*
626 * 0.24 format for fraction, first five bits zeroed
627 */
628 init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
629 init_int = dc_fixpt_floor(data->inits.h);
630 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
631 SCL_H_INIT_FRAC, init_frac,
632 SCL_H_INIT_INT, init_int);
633
634 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
635 init_int = dc_fixpt_floor(data->inits.h_c);
636 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
637 SCL_H_INIT_FRAC_C, init_frac,
638 SCL_H_INIT_INT_C, init_int);
639
640 init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
641 init_int = dc_fixpt_floor(data->inits.v);
642 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
643 SCL_V_INIT_FRAC, init_frac,
644 SCL_V_INIT_INT, init_int);
645
646 if (REG(SCL_VERT_FILTER_INIT_BOT)) {
647 struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
648
649 init_frac = dc_fixpt_u0d19(bot) << 5;
650 init_int = dc_fixpt_floor(bot);
651 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
652 SCL_V_INIT_FRAC_BOT, init_frac,
653 SCL_V_INIT_INT_BOT, init_int);
654 }
655
656 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
657 init_int = dc_fixpt_floor(data->inits.v_c);
658 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
659 SCL_V_INIT_FRAC_C, init_frac,
660 SCL_V_INIT_INT_C, init_int);
661
662 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
663 struct fixed31_32 bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
664
665 init_frac = dc_fixpt_u0d19(bot) << 5;
666 init_int = dc_fixpt_floor(bot);
667 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
668 SCL_V_INIT_FRAC_BOT_C, init_frac,
669 SCL_V_INIT_INT_BOT_C, init_int);
670 }
671 }
672
673 /**
674 * dpp1_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area
675 *
676 * @dpp: DPP data struct
677 * @recount: Rectangle information
678 *
679 * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on
680 * the values specified in the recount parameter.
681 *
682 * Note: This function only have effect if AutoCal is disabled.
683 */
dpp1_dscl_set_recout(struct dcn10_dpp * dpp,const struct rect * recout)684 static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,
685 const struct rect *recout)
686 {
687 int visual_confirm_on = 0;
688 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
689 visual_confirm_on = 1;
690
691 REG_SET_2(RECOUT_START, 0,
692 /* First pixel of RECOUT in the active OTG area */
693 RECOUT_START_X, recout->x,
694 /* First line of RECOUT in the active OTG area */
695 RECOUT_START_Y, recout->y);
696
697 REG_SET_2(RECOUT_SIZE, 0,
698 /* Number of RECOUT horizontal pixels */
699 RECOUT_WIDTH, recout->width,
700 /* Number of RECOUT vertical lines */
701 RECOUT_HEIGHT, recout->height
702 - visual_confirm_on * 2 * (dpp->base.inst + 1));
703 }
704
705 /**
706 * dpp1_dscl_set_scaler_manual_scale - Manually program scaler and line buffer
707 *
708 * @dpp_base: High level DPP struct
709 * @scl_data: scalaer_data info
710 *
711 * This is the primary function to program scaler and line buffer in manual
712 * scaling mode. To execute the required operations for manual scale, we need
713 * to disable AutoCal first.
714 */
dpp1_dscl_set_scaler_manual_scale(struct dpp * dpp_base,const struct scaler_data * scl_data)715 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,
716 const struct scaler_data *scl_data)
717 {
718 enum lb_memory_config lb_config;
719 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
720 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
721 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
722 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
723 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
724
725 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
726 return;
727
728 PERF_TRACE();
729
730 dpp->scl_data = *scl_data;
731
732 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {
733 if (dscl_mode != DSCL_MODE_DSCL_BYPASS)
734 dpp1_power_on_dscl(dpp_base, true);
735 }
736
737 /* Autocal off */
738 REG_SET_3(DSCL_AUTOCAL, 0,
739 AUTOCAL_MODE, AUTOCAL_MODE_OFF,
740 AUTOCAL_NUM_PIPE, 0,
741 AUTOCAL_PIPE_ID, 0);
742
743 /* Recout */
744 dpp1_dscl_set_recout(dpp, &scl_data->recout);
745
746 /* MPC Size */
747 REG_SET_2(MPC_SIZE, 0,
748 /* Number of horizontal pixels of MPC */
749 MPC_WIDTH, scl_data->h_active,
750 /* Number of vertical lines of MPC */
751 MPC_HEIGHT, scl_data->v_active);
752
753 /* SCL mode */
754 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
755
756 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) {
757 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)
758 dpp1_power_on_dscl(dpp_base, false);
759 return;
760 }
761
762 /* LB */
763 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
764 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
765
766 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
767 return;
768
769 /* Black offsets */
770 if (REG(SCL_BLACK_OFFSET)) {
771 if (ycbcr)
772 REG_SET_2(SCL_BLACK_OFFSET, 0,
773 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
774 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
775 else
776
777 REG_SET_2(SCL_BLACK_OFFSET, 0,
778 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
779 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
780 }
781
782 /* Manually calculate scale ratio and init values */
783 dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
784
785 /* HTaps/VTaps */
786 REG_SET_4(SCL_TAP_CONTROL, 0,
787 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
788 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
789 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
790 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
791
792 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
793 PERF_TRACE();
794 }
795