1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
5 * Tiffany Lin <tiffany.lin@mediatek.com>
6 */
7
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of.h>
14 #include <media/v4l2-event.h>
15 #include <media/v4l2-mem2mem.h>
16 #include <media/videobuf2-dma-contig.h>
17 #include <linux/pm_runtime.h>
18
19 #include "mtk_vcodec_drv.h"
20 #include "mtk_vcodec_enc.h"
21 #include "mtk_vcodec_enc_pm.h"
22 #include "mtk_vcodec_intr.h"
23 #include "mtk_vcodec_util.h"
24 #include "mtk_vcodec_fw.h"
25
26 module_param(mtk_v4l2_dbg_level, int, S_IRUGO | S_IWUSR);
27 module_param(mtk_vcodec_dbg, bool, S_IRUGO | S_IWUSR);
28
29 static const struct mtk_video_fmt mtk_video_formats_output[] = {
30 {
31 .fourcc = V4L2_PIX_FMT_NV12M,
32 .type = MTK_FMT_FRAME,
33 .num_planes = 2,
34 },
35 {
36 .fourcc = V4L2_PIX_FMT_NV21M,
37 .type = MTK_FMT_FRAME,
38 .num_planes = 2,
39 },
40 {
41 .fourcc = V4L2_PIX_FMT_YUV420M,
42 .type = MTK_FMT_FRAME,
43 .num_planes = 3,
44 },
45 {
46 .fourcc = V4L2_PIX_FMT_YVU420M,
47 .type = MTK_FMT_FRAME,
48 .num_planes = 3,
49 },
50 };
51
52 static const struct mtk_video_fmt mtk_video_formats_capture_h264[] = {
53 {
54 .fourcc = V4L2_PIX_FMT_H264,
55 .type = MTK_FMT_ENC,
56 .num_planes = 1,
57 },
58 };
59
60 static const struct mtk_video_fmt mtk_video_formats_capture_vp8[] = {
61 {
62 .fourcc = V4L2_PIX_FMT_VP8,
63 .type = MTK_FMT_ENC,
64 .num_planes = 1,
65 },
66 };
67
68 /* Wake up context wait_queue */
wake_up_ctx(struct mtk_vcodec_ctx * ctx,unsigned int reason)69 static void wake_up_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason)
70 {
71 ctx->int_cond = 1;
72 ctx->int_type = reason;
73 wake_up_interruptible(&ctx->queue);
74 }
75
clean_irq_status(unsigned int irq_status,void __iomem * addr)76 static void clean_irq_status(unsigned int irq_status, void __iomem *addr)
77 {
78 if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE)
79 writel(MTK_VENC_IRQ_STATUS_PAUSE, addr);
80
81 if (irq_status & MTK_VENC_IRQ_STATUS_SWITCH)
82 writel(MTK_VENC_IRQ_STATUS_SWITCH, addr);
83
84 if (irq_status & MTK_VENC_IRQ_STATUS_DRAM)
85 writel(MTK_VENC_IRQ_STATUS_DRAM, addr);
86
87 if (irq_status & MTK_VENC_IRQ_STATUS_SPS)
88 writel(MTK_VENC_IRQ_STATUS_SPS, addr);
89
90 if (irq_status & MTK_VENC_IRQ_STATUS_PPS)
91 writel(MTK_VENC_IRQ_STATUS_PPS, addr);
92
93 if (irq_status & MTK_VENC_IRQ_STATUS_FRM)
94 writel(MTK_VENC_IRQ_STATUS_FRM, addr);
95
96 }
mtk_vcodec_enc_irq_handler(int irq,void * priv)97 static irqreturn_t mtk_vcodec_enc_irq_handler(int irq, void *priv)
98 {
99 struct mtk_vcodec_dev *dev = priv;
100 struct mtk_vcodec_ctx *ctx;
101 unsigned long flags;
102 void __iomem *addr;
103
104 spin_lock_irqsave(&dev->irqlock, flags);
105 ctx = dev->curr_ctx;
106 spin_unlock_irqrestore(&dev->irqlock, flags);
107
108 mtk_v4l2_debug(1, "id=%d coreid:%d", ctx->id, dev->venc_pdata->core_id);
109 addr = dev->reg_base[dev->venc_pdata->core_id] +
110 MTK_VENC_IRQ_ACK_OFFSET;
111
112 ctx->irq_status = readl(dev->reg_base[dev->venc_pdata->core_id] +
113 (MTK_VENC_IRQ_STATUS_OFFSET));
114
115 clean_irq_status(ctx->irq_status, addr);
116
117 wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED);
118 return IRQ_HANDLED;
119 }
120
fops_vcodec_open(struct file * file)121 static int fops_vcodec_open(struct file *file)
122 {
123 struct mtk_vcodec_dev *dev = video_drvdata(file);
124 struct mtk_vcodec_ctx *ctx = NULL;
125 int ret = 0;
126 struct vb2_queue *src_vq;
127
128 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
129 if (!ctx)
130 return -ENOMEM;
131
132 mutex_lock(&dev->dev_mutex);
133 /*
134 * Use simple counter to uniquely identify this context. Only
135 * used for logging.
136 */
137 ctx->id = dev->id_counter++;
138 v4l2_fh_init(&ctx->fh, video_devdata(file));
139 file->private_data = &ctx->fh;
140 v4l2_fh_add(&ctx->fh);
141 INIT_LIST_HEAD(&ctx->list);
142 ctx->dev = dev;
143 init_waitqueue_head(&ctx->queue);
144
145 ctx->type = MTK_INST_ENCODER;
146 ret = mtk_vcodec_enc_ctrls_setup(ctx);
147 if (ret) {
148 mtk_v4l2_err("Failed to setup controls() (%d)",
149 ret);
150 goto err_ctrls_setup;
151 }
152 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev_enc, ctx,
153 &mtk_vcodec_enc_queue_init);
154 if (IS_ERR((__force void *)ctx->m2m_ctx)) {
155 ret = PTR_ERR((__force void *)ctx->m2m_ctx);
156 mtk_v4l2_err("Failed to v4l2_m2m_ctx_init() (%d)",
157 ret);
158 goto err_m2m_ctx_init;
159 }
160 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx,
161 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
162 ctx->empty_flush_buf.vb.vb2_buf.vb2_queue = src_vq;
163 mtk_vcodec_enc_set_default_params(ctx);
164
165 if (v4l2_fh_is_singular(&ctx->fh)) {
166 /*
167 * load fireware to checks if it was loaded already and
168 * does nothing in that case
169 */
170 ret = mtk_vcodec_fw_load_firmware(dev->fw_handler);
171 if (ret < 0) {
172 /*
173 * Return 0 if downloading firmware successfully,
174 * otherwise it is failed
175 */
176 mtk_v4l2_err("vpu_load_firmware failed!");
177 goto err_load_fw;
178 }
179
180 dev->enc_capability =
181 mtk_vcodec_fw_get_venc_capa(dev->fw_handler);
182 mtk_v4l2_debug(0, "encoder capability %x", dev->enc_capability);
183 }
184
185 mtk_v4l2_debug(2, "Create instance [%d]@%p m2m_ctx=%p ",
186 ctx->id, ctx, ctx->m2m_ctx);
187
188 list_add(&ctx->list, &dev->ctx_list);
189
190 mutex_unlock(&dev->dev_mutex);
191 mtk_v4l2_debug(0, "%s encoder [%d]", dev_name(&dev->plat_dev->dev),
192 ctx->id);
193 return ret;
194
195 /* Deinit when failure occurred */
196 err_load_fw:
197 v4l2_m2m_ctx_release(ctx->m2m_ctx);
198 err_m2m_ctx_init:
199 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
200 err_ctrls_setup:
201 v4l2_fh_del(&ctx->fh);
202 v4l2_fh_exit(&ctx->fh);
203 kfree(ctx);
204 mutex_unlock(&dev->dev_mutex);
205
206 return ret;
207 }
208
fops_vcodec_release(struct file * file)209 static int fops_vcodec_release(struct file *file)
210 {
211 struct mtk_vcodec_dev *dev = video_drvdata(file);
212 struct mtk_vcodec_ctx *ctx = fh_to_ctx(file->private_data);
213
214 mtk_v4l2_debug(1, "[%d] encoder", ctx->id);
215 mutex_lock(&dev->dev_mutex);
216
217 mtk_vcodec_enc_release(ctx);
218 v4l2_fh_del(&ctx->fh);
219 v4l2_fh_exit(&ctx->fh);
220 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
221 v4l2_m2m_ctx_release(ctx->m2m_ctx);
222
223 list_del_init(&ctx->list);
224 kfree(ctx);
225 mutex_unlock(&dev->dev_mutex);
226 return 0;
227 }
228
229 static const struct v4l2_file_operations mtk_vcodec_fops = {
230 .owner = THIS_MODULE,
231 .open = fops_vcodec_open,
232 .release = fops_vcodec_release,
233 .poll = v4l2_m2m_fop_poll,
234 .unlocked_ioctl = video_ioctl2,
235 .mmap = v4l2_m2m_fop_mmap,
236 };
237
mtk_vcodec_probe(struct platform_device * pdev)238 static int mtk_vcodec_probe(struct platform_device *pdev)
239 {
240 struct mtk_vcodec_dev *dev;
241 struct video_device *vfd_enc;
242 struct resource *res;
243 phandle rproc_phandle;
244 enum mtk_vcodec_fw_type fw_type;
245 int ret;
246
247 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
248 if (!dev)
249 return -ENOMEM;
250
251 INIT_LIST_HEAD(&dev->ctx_list);
252 dev->plat_dev = pdev;
253
254 if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu",
255 &rproc_phandle)) {
256 fw_type = VPU;
257 } else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
258 &rproc_phandle)) {
259 fw_type = SCP;
260 } else {
261 mtk_v4l2_err("Could not get venc IPI device");
262 return -ENODEV;
263 }
264 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
265
266 dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, ENCODER);
267 if (IS_ERR(dev->fw_handler))
268 return PTR_ERR(dev->fw_handler);
269
270 dev->venc_pdata = of_device_get_match_data(&pdev->dev);
271 ret = mtk_vcodec_init_enc_pm(dev);
272 if (ret < 0) {
273 dev_err(&pdev->dev, "Failed to get mtk vcodec clock source!");
274 goto err_enc_pm;
275 }
276
277 pm_runtime_enable(&pdev->dev);
278
279 dev->reg_base[dev->venc_pdata->core_id] =
280 devm_platform_ioremap_resource(pdev, 0);
281 if (IS_ERR(dev->reg_base[dev->venc_pdata->core_id])) {
282 ret = PTR_ERR(dev->reg_base[dev->venc_pdata->core_id]);
283 goto err_res;
284 }
285
286 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
287 if (res == NULL) {
288 dev_err(&pdev->dev, "failed to get irq resource");
289 ret = -ENOENT;
290 goto err_res;
291 }
292
293 dev->enc_irq = platform_get_irq(pdev, 0);
294 irq_set_status_flags(dev->enc_irq, IRQ_NOAUTOEN);
295 ret = devm_request_irq(&pdev->dev, dev->enc_irq,
296 mtk_vcodec_enc_irq_handler,
297 0, pdev->name, dev);
298 if (ret) {
299 dev_err(&pdev->dev,
300 "Failed to install dev->enc_irq %d (%d) core_id (%d)",
301 dev->enc_irq, ret, dev->venc_pdata->core_id);
302 ret = -EINVAL;
303 goto err_res;
304 }
305
306 mutex_init(&dev->enc_mutex);
307 mutex_init(&dev->dev_mutex);
308 spin_lock_init(&dev->irqlock);
309
310 snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s",
311 "[MTK_V4L2_VENC]");
312
313 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
314 if (ret) {
315 mtk_v4l2_err("v4l2_device_register err=%d", ret);
316 goto err_res;
317 }
318
319 init_waitqueue_head(&dev->queue);
320
321 /* allocate video device for encoder and register it */
322 vfd_enc = video_device_alloc();
323 if (!vfd_enc) {
324 mtk_v4l2_err("Failed to allocate video device");
325 ret = -ENOMEM;
326 goto err_enc_alloc;
327 }
328 vfd_enc->fops = &mtk_vcodec_fops;
329 vfd_enc->ioctl_ops = &mtk_venc_ioctl_ops;
330 vfd_enc->release = video_device_release;
331 vfd_enc->lock = &dev->dev_mutex;
332 vfd_enc->v4l2_dev = &dev->v4l2_dev;
333 vfd_enc->vfl_dir = VFL_DIR_M2M;
334 vfd_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE |
335 V4L2_CAP_STREAMING;
336
337 snprintf(vfd_enc->name, sizeof(vfd_enc->name), "%s",
338 MTK_VCODEC_ENC_NAME);
339 video_set_drvdata(vfd_enc, dev);
340 dev->vfd_enc = vfd_enc;
341 platform_set_drvdata(pdev, dev);
342
343 dev->m2m_dev_enc = v4l2_m2m_init(&mtk_venc_m2m_ops);
344 if (IS_ERR((__force void *)dev->m2m_dev_enc)) {
345 mtk_v4l2_err("Failed to init mem2mem enc device");
346 ret = PTR_ERR((__force void *)dev->m2m_dev_enc);
347 goto err_enc_mem_init;
348 }
349
350 dev->encode_workqueue =
351 alloc_ordered_workqueue(MTK_VCODEC_ENC_NAME,
352 WQ_MEM_RECLAIM |
353 WQ_FREEZABLE);
354 if (!dev->encode_workqueue) {
355 mtk_v4l2_err("Failed to create encode workqueue");
356 ret = -EINVAL;
357 goto err_event_workq;
358 }
359
360 if (of_get_property(pdev->dev.of_node, "dma-ranges", NULL))
361 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
362
363 ret = video_register_device(vfd_enc, VFL_TYPE_VIDEO, 1);
364 if (ret) {
365 mtk_v4l2_err("Failed to register video device");
366 goto err_enc_reg;
367 }
368
369 mtk_v4l2_debug(0, "encoder %d registered as /dev/video%d",
370 dev->venc_pdata->core_id, vfd_enc->num);
371
372 return 0;
373
374 err_enc_reg:
375 destroy_workqueue(dev->encode_workqueue);
376 err_event_workq:
377 v4l2_m2m_release(dev->m2m_dev_enc);
378 err_enc_mem_init:
379 video_unregister_device(vfd_enc);
380 err_enc_alloc:
381 v4l2_device_unregister(&dev->v4l2_dev);
382 err_res:
383 mtk_vcodec_release_enc_pm(dev);
384 err_enc_pm:
385 mtk_vcodec_fw_release(dev->fw_handler);
386 return ret;
387 }
388
389 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
390 .chip = MTK_MT8173,
391 .capture_formats = mtk_video_formats_capture_h264,
392 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
393 .output_formats = mtk_video_formats_output,
394 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
395 .min_bitrate = 64,
396 .max_bitrate = 60000000,
397 .core_id = VENC_SYS,
398 };
399
400 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
401 .chip = MTK_MT8173,
402 .capture_formats = mtk_video_formats_capture_vp8,
403 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_vp8),
404 .output_formats = mtk_video_formats_output,
405 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
406 .min_bitrate = 64,
407 .max_bitrate = 9000000,
408 .core_id = VENC_LT_SYS,
409 };
410
411 static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
412 .chip = MTK_MT8183,
413 .uses_ext = true,
414 .capture_formats = mtk_video_formats_capture_h264,
415 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
416 .output_formats = mtk_video_formats_output,
417 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
418 .min_bitrate = 64,
419 .max_bitrate = 40000000,
420 .core_id = VENC_SYS,
421 };
422
423 static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
424 .chip = MTK_MT8192,
425 .uses_ext = true,
426 .capture_formats = mtk_video_formats_capture_h264,
427 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
428 .output_formats = mtk_video_formats_output,
429 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
430 .min_bitrate = 64,
431 .max_bitrate = 100000000,
432 .core_id = VENC_SYS,
433 };
434
435 static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
436 .chip = MTK_MT8195,
437 .uses_ext = true,
438 .capture_formats = mtk_video_formats_capture_h264,
439 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
440 .output_formats = mtk_video_formats_output,
441 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
442 .min_bitrate = 64,
443 .max_bitrate = 100000000,
444 .core_id = VENC_SYS,
445 };
446
447 static const struct of_device_id mtk_vcodec_enc_match[] = {
448 {.compatible = "mediatek,mt8173-vcodec-enc",
449 .data = &mt8173_avc_pdata},
450 {.compatible = "mediatek,mt8173-vcodec-enc-vp8",
451 .data = &mt8173_vp8_pdata},
452 {.compatible = "mediatek,mt8183-vcodec-enc", .data = &mt8183_pdata},
453 {.compatible = "mediatek,mt8192-vcodec-enc", .data = &mt8192_pdata},
454 {.compatible = "mediatek,mt8195-vcodec-enc", .data = &mt8195_pdata},
455 {},
456 };
457 MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match);
458
mtk_vcodec_enc_remove(struct platform_device * pdev)459 static int mtk_vcodec_enc_remove(struct platform_device *pdev)
460 {
461 struct mtk_vcodec_dev *dev = platform_get_drvdata(pdev);
462
463 mtk_v4l2_debug_enter();
464 flush_workqueue(dev->encode_workqueue);
465 destroy_workqueue(dev->encode_workqueue);
466 if (dev->m2m_dev_enc)
467 v4l2_m2m_release(dev->m2m_dev_enc);
468
469 if (dev->vfd_enc)
470 video_unregister_device(dev->vfd_enc);
471
472 v4l2_device_unregister(&dev->v4l2_dev);
473 mtk_vcodec_release_enc_pm(dev);
474 mtk_vcodec_fw_release(dev->fw_handler);
475 return 0;
476 }
477
478 static struct platform_driver mtk_vcodec_enc_driver = {
479 .probe = mtk_vcodec_probe,
480 .remove = mtk_vcodec_enc_remove,
481 .driver = {
482 .name = MTK_VCODEC_ENC_NAME,
483 .of_match_table = mtk_vcodec_enc_match,
484 },
485 };
486
487 module_platform_driver(mtk_vcodec_enc_driver);
488
489
490 MODULE_LICENSE("GPL v2");
491 MODULE_DESCRIPTION("Mediatek video codec V4L2 encoder driver");
492