1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RPC-IF core driver
4 *
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
6 * Copyright (C) 2019 Macronix International Co., Ltd.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17
18 #include <memory/renesas-rpc-if.h>
19
20 #define RPCIF_CMNCR 0x0000 /* R/W */
21 #define RPCIF_CMNCR_MD BIT(31)
22 #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
27 #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
28 RPCIF_CMNCR_MOIIO1(3) | \
29 RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
30 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
31 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
32 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
33 #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
34 RPCIF_CMNCR_IO3FV(3))
35 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
36
37 #define RPCIF_SSLDR 0x0004 /* R/W */
38 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
39 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
40 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
41
42 #define RPCIF_DRCR 0x000C /* R/W */
43 #define RPCIF_DRCR_SSLN BIT(24)
44 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
45 #define RPCIF_DRCR_RCF BIT(9)
46 #define RPCIF_DRCR_RBE BIT(8)
47 #define RPCIF_DRCR_SSLE BIT(0)
48
49 #define RPCIF_DRCMR 0x0010 /* R/W */
50 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
51 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
52
53 #define RPCIF_DREAR 0x0014 /* R/W */
54 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
55 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
56
57 #define RPCIF_DROPR 0x0018 /* R/W */
58
59 #define RPCIF_DRENR 0x001C /* R/W */
60 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
61 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
62 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
63 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
64 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
65 #define RPCIF_DRENR_DME BIT(15)
66 #define RPCIF_DRENR_CDE BIT(14)
67 #define RPCIF_DRENR_OCDE BIT(12)
68 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
69 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
70
71 #define RPCIF_SMCR 0x0020 /* R/W */
72 #define RPCIF_SMCR_SSLKP BIT(8)
73 #define RPCIF_SMCR_SPIRE BIT(2)
74 #define RPCIF_SMCR_SPIWE BIT(1)
75 #define RPCIF_SMCR_SPIE BIT(0)
76
77 #define RPCIF_SMCMR 0x0024 /* R/W */
78 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
79 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
80
81 #define RPCIF_SMADR 0x0028 /* R/W */
82
83 #define RPCIF_SMOPR 0x002C /* R/W */
84 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
85 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
86 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
87 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
88
89 #define RPCIF_SMENR 0x0030 /* R/W */
90 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
91 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
92 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
93 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
94 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
95 #define RPCIF_SMENR_DME BIT(15)
96 #define RPCIF_SMENR_CDE BIT(14)
97 #define RPCIF_SMENR_OCDE BIT(12)
98 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
99 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
100 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
101
102 #define RPCIF_SMRDR0 0x0038 /* R */
103 #define RPCIF_SMRDR1 0x003C /* R */
104 #define RPCIF_SMWDR0 0x0040 /* W */
105 #define RPCIF_SMWDR1 0x0044 /* W */
106
107 #define RPCIF_CMNSR 0x0048 /* R */
108 #define RPCIF_CMNSR_SSLF BIT(1)
109 #define RPCIF_CMNSR_TEND BIT(0)
110
111 #define RPCIF_DRDMCR 0x0058 /* R/W */
112 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
113
114 #define RPCIF_DRDRENR 0x005C /* R/W */
115 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
116 #define RPCIF_DRDRENR_ADDRE BIT(8)
117 #define RPCIF_DRDRENR_OPDRE BIT(4)
118 #define RPCIF_DRDRENR_DRDRE BIT(0)
119
120 #define RPCIF_SMDMCR 0x0060 /* R/W */
121 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
122
123 #define RPCIF_SMDRENR 0x0064 /* R/W */
124 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
125 #define RPCIF_SMDRENR_ADDRE BIT(8)
126 #define RPCIF_SMDRENR_OPDRE BIT(4)
127 #define RPCIF_SMDRENR_SPIDRE BIT(0)
128
129 #define RPCIF_PHYCNT 0x007C /* R/W */
130 #define RPCIF_PHYCNT_CAL BIT(31)
131 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
132 #define RPCIF_PHYCNT_EXDS BIT(21)
133 #define RPCIF_PHYCNT_OCT BIT(20)
134 #define RPCIF_PHYCNT_DDRCAL BIT(19)
135 #define RPCIF_PHYCNT_HS BIT(18)
136 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
137 #define RPCIF_PHYCNT_WBUF2 BIT(4)
138 #define RPCIF_PHYCNT_WBUF BIT(2)
139 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
140
141 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
142 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
143
144 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
145 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
146
147 #define RPCIF_PHYINT 0x0088 /* R/W */
148 #define RPCIF_PHYINT_WPVAL BIT(1)
149
150 #define RPCIF_DIRMAP_SIZE 0x4000000
151
152 static const struct regmap_range rpcif_volatile_ranges[] = {
153 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
154 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
155 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
156 };
157
158 static const struct regmap_access_table rpcif_volatile_table = {
159 .yes_ranges = rpcif_volatile_ranges,
160 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
161 };
162
163
164 /*
165 * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
166 * with proper width. Requires SMENR_SPIDE to be correctly set before!
167 */
rpcif_reg_read(void * context,unsigned int reg,unsigned int * val)168 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
169 {
170 struct rpcif *rpc = context;
171
172 if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
173 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
174
175 if (spide == 0x8) {
176 *val = readb(rpc->base + reg);
177 return 0;
178 } else if (spide == 0xC) {
179 *val = readw(rpc->base + reg);
180 return 0;
181 } else if (spide != 0xF) {
182 return -EILSEQ;
183 }
184 }
185
186 *val = readl(rpc->base + reg);
187 return 0;
188 }
189
rpcif_reg_write(void * context,unsigned int reg,unsigned int val)190 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
191 {
192 struct rpcif *rpc = context;
193
194 if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
195 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
196
197 if (spide == 0x8) {
198 writeb(val, rpc->base + reg);
199 return 0;
200 } else if (spide == 0xC) {
201 writew(val, rpc->base + reg);
202 return 0;
203 } else if (spide != 0xF) {
204 return -EILSEQ;
205 }
206 }
207
208 writel(val, rpc->base + reg);
209 return 0;
210 }
211
212 static const struct regmap_config rpcif_regmap_config = {
213 .reg_bits = 32,
214 .val_bits = 32,
215 .reg_stride = 4,
216 .reg_read = rpcif_reg_read,
217 .reg_write = rpcif_reg_write,
218 .fast_io = true,
219 .max_register = RPCIF_PHYINT,
220 .volatile_table = &rpcif_volatile_table,
221 };
222
rpcif_sw_init(struct rpcif * rpc,struct device * dev)223 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
224 {
225 struct platform_device *pdev = to_platform_device(dev);
226 struct resource *res;
227
228 rpc->dev = dev;
229
230 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
231 rpc->base = devm_ioremap_resource(&pdev->dev, res);
232 if (IS_ERR(rpc->base))
233 return PTR_ERR(rpc->base);
234
235 rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
236 if (IS_ERR(rpc->regmap)) {
237 dev_err(&pdev->dev,
238 "failed to init regmap for rpcif, error %ld\n",
239 PTR_ERR(rpc->regmap));
240 return PTR_ERR(rpc->regmap);
241 }
242
243 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
244 rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
245 if (IS_ERR(rpc->dirmap))
246 rpc->dirmap = NULL;
247 rpc->size = resource_size(res);
248
249 rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
250
251 return PTR_ERR_OR_ZERO(rpc->rstc);
252 }
253 EXPORT_SYMBOL(rpcif_sw_init);
254
rpcif_hw_init(struct rpcif * rpc,bool hyperflash)255 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
256 {
257 u32 dummy;
258
259 pm_runtime_get_sync(rpc->dev);
260
261 /*
262 * NOTE: The 0x260 are undocumented bits, but they must be set.
263 * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
264 * 0x0 : the delay is biggest,
265 * 0x1 : the delay is 2nd biggest,
266 * On H3 ES1.x, the value should be 0, while on others,
267 * the value should be 7.
268 */
269 regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
270 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
271
272 /*
273 * NOTE: The 0x1511144 are undocumented bits, but they must be set
274 * for RPCIF_PHYOFFSET1.
275 * The 0x31 are undocumented bits, but they must be set
276 * for RPCIF_PHYOFFSET2.
277 */
278 regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
279 RPCIF_PHYOFFSET1_DDRTMG(3));
280 regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
281 RPCIF_PHYOFFSET2_OCTTMG(4));
282
283 if (hyperflash)
284 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
285 RPCIF_PHYINT_WPVAL, 0);
286
287 regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
288 RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
289 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
290 /* Set RCF after BSZ update */
291 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
292 /* Dummy read according to spec */
293 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
294 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
295 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
296
297 pm_runtime_put(rpc->dev);
298
299 rpc->bus_size = hyperflash ? 2 : 1;
300 }
301 EXPORT_SYMBOL(rpcif_hw_init);
302
wait_msg_xfer_end(struct rpcif * rpc)303 static int wait_msg_xfer_end(struct rpcif *rpc)
304 {
305 u32 sts;
306
307 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
308 sts & RPCIF_CMNSR_TEND, 0,
309 USEC_PER_SEC);
310 }
311
rpcif_bits_set(struct rpcif * rpc,u32 nbytes)312 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
313 {
314 if (rpc->bus_size == 2)
315 nbytes /= 2;
316 nbytes = clamp(nbytes, 1U, 4U);
317 return GENMASK(3, 4 - nbytes);
318 }
319
rpcif_bit_size(u8 buswidth)320 static u8 rpcif_bit_size(u8 buswidth)
321 {
322 return buswidth > 4 ? 2 : ilog2(buswidth);
323 }
324
rpcif_prepare(struct rpcif * rpc,const struct rpcif_op * op,u64 * offs,size_t * len)325 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
326 size_t *len)
327 {
328 rpc->smcr = 0;
329 rpc->smadr = 0;
330 rpc->enable = 0;
331 rpc->command = 0;
332 rpc->option = 0;
333 rpc->dummy = 0;
334 rpc->ddr = 0;
335 rpc->xferlen = 0;
336
337 if (op->cmd.buswidth) {
338 rpc->enable = RPCIF_SMENR_CDE |
339 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
340 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
341 if (op->cmd.ddr)
342 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
343 }
344 if (op->ocmd.buswidth) {
345 rpc->enable |= RPCIF_SMENR_OCDE |
346 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
347 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
348 }
349
350 if (op->addr.buswidth) {
351 rpc->enable |=
352 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
353 if (op->addr.nbytes == 4)
354 rpc->enable |= RPCIF_SMENR_ADE(0xF);
355 else
356 rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
357 2, 3 - op->addr.nbytes));
358 if (op->addr.ddr)
359 rpc->ddr |= RPCIF_SMDRENR_ADDRE;
360
361 if (offs && len)
362 rpc->smadr = *offs;
363 else
364 rpc->smadr = op->addr.val;
365 }
366
367 if (op->dummy.buswidth) {
368 rpc->enable |= RPCIF_SMENR_DME;
369 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
370 op->dummy.buswidth);
371 }
372
373 if (op->option.buswidth) {
374 rpc->enable |= RPCIF_SMENR_OPDE(
375 rpcif_bits_set(rpc, op->option.nbytes)) |
376 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
377 if (op->option.ddr)
378 rpc->ddr |= RPCIF_SMDRENR_OPDRE;
379 rpc->option = op->option.val;
380 }
381
382 rpc->dir = op->data.dir;
383 if (op->data.buswidth) {
384 u32 nbytes;
385
386 rpc->buffer = op->data.buf.in;
387 switch (op->data.dir) {
388 case RPCIF_DATA_IN:
389 rpc->smcr = RPCIF_SMCR_SPIRE;
390 break;
391 case RPCIF_DATA_OUT:
392 rpc->smcr = RPCIF_SMCR_SPIWE;
393 break;
394 default:
395 break;
396 }
397 if (op->data.ddr)
398 rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
399
400 if (offs && len)
401 nbytes = *len;
402 else
403 nbytes = op->data.nbytes;
404 rpc->xferlen = nbytes;
405
406 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
407 }
408 }
409 EXPORT_SYMBOL(rpcif_prepare);
410
rpcif_manual_xfer(struct rpcif * rpc)411 int rpcif_manual_xfer(struct rpcif *rpc)
412 {
413 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
414 int ret = 0;
415
416 pm_runtime_get_sync(rpc->dev);
417
418 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
419 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
420 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
421 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
422 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
423 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
424 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
425 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
426 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
427 smenr = rpc->enable;
428
429 switch (rpc->dir) {
430 case RPCIF_DATA_OUT:
431 while (pos < rpc->xferlen) {
432 u32 bytes_left = rpc->xferlen - pos;
433 u32 nbytes, data[2];
434
435 smcr = rpc->smcr | RPCIF_SMCR_SPIE;
436
437 /* nbytes may only be 1, 2, 4, or 8 */
438 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
439 if (bytes_left > nbytes)
440 smcr |= RPCIF_SMCR_SSLKP;
441
442 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
443 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
444
445 memcpy(data, rpc->buffer + pos, nbytes);
446 if (nbytes == 8) {
447 regmap_write(rpc->regmap, RPCIF_SMWDR1,
448 data[0]);
449 regmap_write(rpc->regmap, RPCIF_SMWDR0,
450 data[1]);
451 } else {
452 regmap_write(rpc->regmap, RPCIF_SMWDR0,
453 data[0]);
454 }
455
456 regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
457 ret = wait_msg_xfer_end(rpc);
458 if (ret)
459 goto err_out;
460
461 pos += nbytes;
462 smenr = rpc->enable &
463 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
464 }
465 break;
466 case RPCIF_DATA_IN:
467 /*
468 * RPC-IF spoils the data for the commands without an address
469 * phase (like RDID) in the manual mode, so we'll have to work
470 * around this issue by using the external address space read
471 * mode instead.
472 */
473 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
474 u32 dummy;
475
476 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
477 RPCIF_CMNCR_MD, 0);
478 regmap_write(rpc->regmap, RPCIF_DRCR,
479 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
480 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
481 regmap_write(rpc->regmap, RPCIF_DREAR,
482 RPCIF_DREAR_EAC(1));
483 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
484 regmap_write(rpc->regmap, RPCIF_DRENR,
485 smenr & ~RPCIF_SMENR_SPIDE(0xF));
486 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
487 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
488 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
489 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
490 /* Dummy read according to spec */
491 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
492 break;
493 }
494 while (pos < rpc->xferlen) {
495 u32 bytes_left = rpc->xferlen - pos;
496 u32 nbytes, data[2];
497
498 /* nbytes may only be 1, 2, 4, or 8 */
499 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
500
501 regmap_write(rpc->regmap, RPCIF_SMADR,
502 rpc->smadr + pos);
503 smenr &= ~RPCIF_SMENR_SPIDE(0xF);
504 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
505 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
506 regmap_write(rpc->regmap, RPCIF_SMCR,
507 rpc->smcr | RPCIF_SMCR_SPIE);
508 ret = wait_msg_xfer_end(rpc);
509 if (ret)
510 goto err_out;
511
512 if (nbytes == 8) {
513 regmap_read(rpc->regmap, RPCIF_SMRDR1,
514 &data[0]);
515 regmap_read(rpc->regmap, RPCIF_SMRDR0,
516 &data[1]);
517 } else {
518 regmap_read(rpc->regmap, RPCIF_SMRDR0,
519 &data[0]);
520 }
521 memcpy(rpc->buffer + pos, data, nbytes);
522
523 pos += nbytes;
524 }
525 break;
526 default:
527 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
528 regmap_write(rpc->regmap, RPCIF_SMCR,
529 rpc->smcr | RPCIF_SMCR_SPIE);
530 ret = wait_msg_xfer_end(rpc);
531 if (ret)
532 goto err_out;
533 }
534
535 exit:
536 pm_runtime_put(rpc->dev);
537 return ret;
538
539 err_out:
540 if (reset_control_reset(rpc->rstc))
541 dev_err(rpc->dev, "Failed to reset HW\n");
542 rpcif_hw_init(rpc, rpc->bus_size == 2);
543 goto exit;
544 }
545 EXPORT_SYMBOL(rpcif_manual_xfer);
546
memcpy_fromio_readw(void * to,const void __iomem * from,size_t count)547 static void memcpy_fromio_readw(void *to,
548 const void __iomem *from,
549 size_t count)
550 {
551 const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
552 u8 buf[2];
553
554 if (count && ((unsigned long)from & 1)) {
555 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
556 *(u8 *)to = buf[1];
557 from++;
558 to++;
559 count--;
560 }
561 while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
562 *(u16 *)to = __raw_readw(from);
563 from += 2;
564 to += 2;
565 count -= 2;
566 }
567 while (count >= maxw) {
568 #ifdef CONFIG_64BIT
569 *(u64 *)to = __raw_readq(from);
570 #else
571 *(u32 *)to = __raw_readl(from);
572 #endif
573 from += maxw;
574 to += maxw;
575 count -= maxw;
576 }
577 while (count >= 2) {
578 *(u16 *)to = __raw_readw(from);
579 from += 2;
580 to += 2;
581 count -= 2;
582 }
583 if (count) {
584 *(u16 *)buf = __raw_readw(from);
585 *(u8 *)to = buf[0];
586 }
587 }
588
rpcif_dirmap_read(struct rpcif * rpc,u64 offs,size_t len,void * buf)589 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
590 {
591 loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
592 size_t size = RPCIF_DIRMAP_SIZE - from;
593
594 if (len > size)
595 len = size;
596
597 pm_runtime_get_sync(rpc->dev);
598
599 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
600 regmap_write(rpc->regmap, RPCIF_DRCR, 0);
601 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
602 regmap_write(rpc->regmap, RPCIF_DREAR,
603 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
604 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
605 regmap_write(rpc->regmap, RPCIF_DRENR,
606 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
607 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
608 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
609
610 if (rpc->bus_size == 2)
611 memcpy_fromio_readw(buf, rpc->dirmap + from, len);
612 else
613 memcpy_fromio(buf, rpc->dirmap + from, len);
614
615 pm_runtime_put(rpc->dev);
616
617 return len;
618 }
619 EXPORT_SYMBOL(rpcif_dirmap_read);
620
rpcif_probe(struct platform_device * pdev)621 static int rpcif_probe(struct platform_device *pdev)
622 {
623 struct platform_device *vdev;
624 struct device_node *flash;
625 const char *name;
626
627 flash = of_get_next_child(pdev->dev.of_node, NULL);
628 if (!flash) {
629 dev_warn(&pdev->dev, "no flash node found\n");
630 return -ENODEV;
631 }
632
633 if (of_device_is_compatible(flash, "jedec,spi-nor")) {
634 name = "rpc-if-spi";
635 } else if (of_device_is_compatible(flash, "cfi-flash")) {
636 name = "rpc-if-hyperflash";
637 } else {
638 of_node_put(flash);
639 dev_warn(&pdev->dev, "unknown flash type\n");
640 return -ENODEV;
641 }
642 of_node_put(flash);
643
644 vdev = platform_device_alloc(name, pdev->id);
645 if (!vdev)
646 return -ENOMEM;
647 vdev->dev.parent = &pdev->dev;
648 platform_set_drvdata(pdev, vdev);
649 return platform_device_add(vdev);
650 }
651
rpcif_remove(struct platform_device * pdev)652 static int rpcif_remove(struct platform_device *pdev)
653 {
654 struct platform_device *vdev = platform_get_drvdata(pdev);
655
656 platform_device_unregister(vdev);
657
658 return 0;
659 }
660
661 static const struct of_device_id rpcif_of_match[] = {
662 { .compatible = "renesas,rcar-gen3-rpc-if", },
663 {},
664 };
665 MODULE_DEVICE_TABLE(of, rpcif_of_match);
666
667 static struct platform_driver rpcif_driver = {
668 .probe = rpcif_probe,
669 .remove = rpcif_remove,
670 .driver = {
671 .name = "rpc-if",
672 .of_match_table = rpcif_of_match,
673 },
674 };
675 module_platform_driver(rpcif_driver);
676
677 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
678 MODULE_LICENSE("GPL v2");
679