1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs
4 *
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8 *
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
11 *
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
18 *
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
26 */
27
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/etherdevice.h>
31 #include <linux/firmware.h>
32 #include <linux/if_bridge.h>
33 #include <linux/if_vlan.h>
34 #include <linux/iopoll.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/module.h>
37 #include <linux/of_mdio.h>
38 #include <linux/of_net.h>
39 #include <linux/of_platform.h>
40 #include <linux/phy.h>
41 #include <linux/phylink.h>
42 #include <linux/platform_device.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
45 #include <net/dsa.h>
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
47
48 #include "lantiq_pce.h"
49
50 /* GSWIP MDIO Registers */
51 #define GSWIP_MDIO_GLOB 0x00
52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15)
53 #define GSWIP_MDIO_CTRL 0x08
54 #define GSWIP_MDIO_CTRL_BUSY BIT(12)
55 #define GSWIP_MDIO_CTRL_RD BIT(11)
56 #define GSWIP_MDIO_CTRL_WR BIT(10)
57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
60 #define GSWIP_MDIO_READ 0x09
61 #define GSWIP_MDIO_WRITE 0x0A
62 #define GSWIP_MDIO_MDC_CFG0 0x0B
63 #define GSWIP_MDIO_MDC_CFG1 0x0C
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000
66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000
69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000
72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800
73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000
74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200
77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
88 GSWIP_MDIO_PHY_FCONRX_MASK | \
89 GSWIP_MDIO_PHY_FCONTX_MASK | \
90 GSWIP_MDIO_PHY_LINK_MASK | \
91 GSWIP_MDIO_PHY_SPEED_MASK | \
92 GSWIP_MDIO_PHY_FDUP_MASK)
93
94 /* GSWIP MII Registers */
95 #define GSWIP_MII_CFGp(p) (0x2 * (p))
96 #define GSWIP_MII_CFG_RESET BIT(15)
97 #define GSWIP_MII_CFG_EN BIT(14)
98 #define GSWIP_MII_CFG_ISOLATE BIT(13)
99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12)
100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8)
101 #define GSWIP_MII_CFG_RMII_CLK BIT(7)
102 #define GSWIP_MII_CFG_MODE_MIIP 0x0
103 #define GSWIP_MII_CFG_MODE_MIIM 0x1
104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2
105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3
106 #define GSWIP_MII_CFG_MODE_RGMII 0x4
107 #define GSWIP_MII_CFG_MODE_GMII 0x9
108 #define GSWIP_MII_CFG_MODE_MASK 0xf
109 #define GSWIP_MII_CFG_RATE_M2P5 0x00
110 #define GSWIP_MII_CFG_RATE_M25 0x10
111 #define GSWIP_MII_CFG_RATE_M125 0x20
112 #define GSWIP_MII_CFG_RATE_M50 0x30
113 #define GSWIP_MII_CFG_RATE_AUTO 0x40
114 #define GSWIP_MII_CFG_RATE_MASK 0x70
115 #define GSWIP_MII_PCDU0 0x01
116 #define GSWIP_MII_PCDU1 0x03
117 #define GSWIP_MII_PCDU5 0x05
118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
120
121 /* GSWIP Core Registers */
122 #define GSWIP_SWRES 0x000
123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
125 #define GSWIP_VERSION 0x013
126 #define GSWIP_VERSION_REV_SHIFT 0
127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
128 #define GSWIP_VERSION_MOD_SHIFT 8
129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
130 #define GSWIP_VERSION_2_0 0x100
131 #define GSWIP_VERSION_2_1 0x021
132 #define GSWIP_VERSION_2_2 0x122
133 #define GSWIP_VERSION_2_2_ETC 0x022
134
135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
136 #define GSWIP_BM_RAM_ADDR 0x044
137 #define GSWIP_BM_RAM_CTRL 0x045
138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15)
139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
141 #define GSWIP_BM_QUEUE_GCTRL 0x04A
142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
143 /* buffer management Port Configuration Register */
144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
147 /* buffer management Port Control Register */
148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
151
152 /* PCE */
153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
154 #define GSWIP_PCE_TBL_MASK 0x448
155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
156 #define GSWIP_PCE_TBL_ADDR 0x44E
157 #define GSWIP_PCE_TBL_CTRL 0x44F
158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
172 #define GSWIP_PCE_GCTRL_0 0x456
173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
176 #define GSWIP_PCE_GCTRL_1 0x457
177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
196
197 #define GSWIP_MAC_FLEN 0x8C5
198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8)
200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
216 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
217
218 /* Ethernet Switch Fetch DMA Port Control Register */
219 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
220 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
221 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
222 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
223 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
224 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
225 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
226 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
227 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
228
229 /* Ethernet Switch Store DMA Port Control Register */
230 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
231 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
232 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
233 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
234
235 #define GSWIP_TABLE_ACTIVE_VLAN 0x01
236 #define GSWIP_TABLE_VLAN_MAPPING 0x02
237 #define GSWIP_TABLE_MAC_BRIDGE 0x0b
238 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
239
240 #define XRX200_GPHY_FW_ALIGN (16 * 1024)
241
242 struct gswip_hw_info {
243 int max_ports;
244 int cpu_port;
245 const struct dsa_switch_ops *ops;
246 };
247
248 struct xway_gphy_match_data {
249 char *fe_firmware_name;
250 char *ge_firmware_name;
251 };
252
253 struct gswip_gphy_fw {
254 struct clk *clk_gate;
255 struct reset_control *reset;
256 u32 fw_addr_offset;
257 char *fw_name;
258 };
259
260 struct gswip_vlan {
261 struct net_device *bridge;
262 u16 vid;
263 u8 fid;
264 };
265
266 struct gswip_priv {
267 __iomem void *gswip;
268 __iomem void *mdio;
269 __iomem void *mii;
270 const struct gswip_hw_info *hw_info;
271 const struct xway_gphy_match_data *gphy_fw_name_cfg;
272 struct dsa_switch *ds;
273 struct device *dev;
274 struct regmap *rcu_regmap;
275 struct gswip_vlan vlans[64];
276 int num_gphy_fw;
277 struct gswip_gphy_fw *gphy_fw;
278 u32 port_vlan_filter;
279 struct mutex pce_table_lock;
280 };
281
282 struct gswip_pce_table_entry {
283 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
284 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
285 u16 key[8];
286 u16 val[5];
287 u16 mask;
288 u8 gmap;
289 bool type;
290 bool valid;
291 bool key_mode;
292 };
293
294 struct gswip_rmon_cnt_desc {
295 unsigned int size;
296 unsigned int offset;
297 const char *name;
298 };
299
300 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
301
302 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
303 /** Receive Packet Count (only packets that are accepted and not discarded). */
304 MIB_DESC(1, 0x1F, "RxGoodPkts"),
305 MIB_DESC(1, 0x23, "RxUnicastPkts"),
306 MIB_DESC(1, 0x22, "RxMulticastPkts"),
307 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
308 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
309 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
310 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
311 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
312 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
313 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
314 MIB_DESC(1, 0x12, "Rx64BytePkts"),
315 MIB_DESC(1, 0x13, "Rx127BytePkts"),
316 MIB_DESC(1, 0x14, "Rx255BytePkts"),
317 MIB_DESC(1, 0x15, "Rx511BytePkts"),
318 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
319 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
320 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
321 MIB_DESC(1, 0x18, "RxDroppedPkts"),
322 MIB_DESC(1, 0x19, "RxFilteredPkts"),
323 MIB_DESC(2, 0x24, "RxGoodBytes"),
324 MIB_DESC(2, 0x26, "RxBadBytes"),
325 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
326 MIB_DESC(1, 0x0C, "TxGoodPkts"),
327 MIB_DESC(1, 0x06, "TxUnicastPkts"),
328 MIB_DESC(1, 0x07, "TxMulticastPkts"),
329 MIB_DESC(1, 0x00, "Tx64BytePkts"),
330 MIB_DESC(1, 0x01, "Tx127BytePkts"),
331 MIB_DESC(1, 0x02, "Tx255BytePkts"),
332 MIB_DESC(1, 0x03, "Tx511BytePkts"),
333 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
334 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
335 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
336 MIB_DESC(1, 0x08, "TxSingleCollCount"),
337 MIB_DESC(1, 0x09, "TxMultCollCount"),
338 MIB_DESC(1, 0x0A, "TxLateCollCount"),
339 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
340 MIB_DESC(1, 0x0D, "TxPauseCount"),
341 MIB_DESC(1, 0x10, "TxDroppedPkts"),
342 MIB_DESC(2, 0x0E, "TxGoodBytes"),
343 };
344
gswip_switch_r(struct gswip_priv * priv,u32 offset)345 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
346 {
347 return __raw_readl(priv->gswip + (offset * 4));
348 }
349
gswip_switch_w(struct gswip_priv * priv,u32 val,u32 offset)350 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
351 {
352 __raw_writel(val, priv->gswip + (offset * 4));
353 }
354
gswip_switch_mask(struct gswip_priv * priv,u32 clear,u32 set,u32 offset)355 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
356 u32 offset)
357 {
358 u32 val = gswip_switch_r(priv, offset);
359
360 val &= ~(clear);
361 val |= set;
362 gswip_switch_w(priv, val, offset);
363 }
364
gswip_switch_r_timeout(struct gswip_priv * priv,u32 offset,u32 cleared)365 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
366 u32 cleared)
367 {
368 u32 val;
369
370 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
371 (val & cleared) == 0, 20, 50000);
372 }
373
gswip_mdio_r(struct gswip_priv * priv,u32 offset)374 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
375 {
376 return __raw_readl(priv->mdio + (offset * 4));
377 }
378
gswip_mdio_w(struct gswip_priv * priv,u32 val,u32 offset)379 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
380 {
381 __raw_writel(val, priv->mdio + (offset * 4));
382 }
383
gswip_mdio_mask(struct gswip_priv * priv,u32 clear,u32 set,u32 offset)384 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
385 u32 offset)
386 {
387 u32 val = gswip_mdio_r(priv, offset);
388
389 val &= ~(clear);
390 val |= set;
391 gswip_mdio_w(priv, val, offset);
392 }
393
gswip_mii_r(struct gswip_priv * priv,u32 offset)394 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
395 {
396 return __raw_readl(priv->mii + (offset * 4));
397 }
398
gswip_mii_w(struct gswip_priv * priv,u32 val,u32 offset)399 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
400 {
401 __raw_writel(val, priv->mii + (offset * 4));
402 }
403
gswip_mii_mask(struct gswip_priv * priv,u32 clear,u32 set,u32 offset)404 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
405 u32 offset)
406 {
407 u32 val = gswip_mii_r(priv, offset);
408
409 val &= ~(clear);
410 val |= set;
411 gswip_mii_w(priv, val, offset);
412 }
413
gswip_mii_mask_cfg(struct gswip_priv * priv,u32 clear,u32 set,int port)414 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
415 int port)
416 {
417 /* There's no MII_CFG register for the CPU port */
418 if (!dsa_is_cpu_port(priv->ds, port))
419 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
420 }
421
gswip_mii_mask_pcdu(struct gswip_priv * priv,u32 clear,u32 set,int port)422 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
423 int port)
424 {
425 switch (port) {
426 case 0:
427 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
428 break;
429 case 1:
430 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
431 break;
432 case 5:
433 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
434 break;
435 }
436 }
437
gswip_mdio_poll(struct gswip_priv * priv)438 static int gswip_mdio_poll(struct gswip_priv *priv)
439 {
440 int cnt = 100;
441
442 while (likely(cnt--)) {
443 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
444
445 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
446 return 0;
447 usleep_range(20, 40);
448 }
449
450 return -ETIMEDOUT;
451 }
452
gswip_mdio_wr(struct mii_bus * bus,int addr,int reg,u16 val)453 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
454 {
455 struct gswip_priv *priv = bus->priv;
456 int err;
457
458 err = gswip_mdio_poll(priv);
459 if (err) {
460 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
461 return err;
462 }
463
464 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
465 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
466 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
467 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
468 GSWIP_MDIO_CTRL);
469
470 return 0;
471 }
472
gswip_mdio_rd(struct mii_bus * bus,int addr,int reg)473 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
474 {
475 struct gswip_priv *priv = bus->priv;
476 int err;
477
478 err = gswip_mdio_poll(priv);
479 if (err) {
480 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
481 return err;
482 }
483
484 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
485 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
486 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
487 GSWIP_MDIO_CTRL);
488
489 err = gswip_mdio_poll(priv);
490 if (err) {
491 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
492 return err;
493 }
494
495 return gswip_mdio_r(priv, GSWIP_MDIO_READ);
496 }
497
gswip_mdio(struct gswip_priv * priv,struct device_node * mdio_np)498 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
499 {
500 struct dsa_switch *ds = priv->ds;
501
502 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev);
503 if (!ds->slave_mii_bus)
504 return -ENOMEM;
505
506 ds->slave_mii_bus->priv = priv;
507 ds->slave_mii_bus->read = gswip_mdio_rd;
508 ds->slave_mii_bus->write = gswip_mdio_wr;
509 ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
510 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
511 dev_name(priv->dev));
512 ds->slave_mii_bus->parent = priv->dev;
513 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
514
515 return of_mdiobus_register(ds->slave_mii_bus, mdio_np);
516 }
517
gswip_pce_table_entry_read(struct gswip_priv * priv,struct gswip_pce_table_entry * tbl)518 static int gswip_pce_table_entry_read(struct gswip_priv *priv,
519 struct gswip_pce_table_entry *tbl)
520 {
521 int i;
522 int err;
523 u16 crtl;
524 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
525 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
526
527 mutex_lock(&priv->pce_table_lock);
528
529 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
530 GSWIP_PCE_TBL_CTRL_BAS);
531 if (err) {
532 mutex_unlock(&priv->pce_table_lock);
533 return err;
534 }
535
536 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
537 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
538 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
539 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
540 GSWIP_PCE_TBL_CTRL);
541
542 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
543 GSWIP_PCE_TBL_CTRL_BAS);
544 if (err) {
545 mutex_unlock(&priv->pce_table_lock);
546 return err;
547 }
548
549 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
550 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
551
552 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
553 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
554
555 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
556
557 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
558
559 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
560 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
561 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
562
563 mutex_unlock(&priv->pce_table_lock);
564
565 return 0;
566 }
567
gswip_pce_table_entry_write(struct gswip_priv * priv,struct gswip_pce_table_entry * tbl)568 static int gswip_pce_table_entry_write(struct gswip_priv *priv,
569 struct gswip_pce_table_entry *tbl)
570 {
571 int i;
572 int err;
573 u16 crtl;
574 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
575 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
576
577 mutex_lock(&priv->pce_table_lock);
578
579 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
580 GSWIP_PCE_TBL_CTRL_BAS);
581 if (err) {
582 mutex_unlock(&priv->pce_table_lock);
583 return err;
584 }
585
586 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
587 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
588 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
589 tbl->table | addr_mode,
590 GSWIP_PCE_TBL_CTRL);
591
592 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
593 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
594
595 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
596 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
597
598 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
599 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
600 tbl->table | addr_mode,
601 GSWIP_PCE_TBL_CTRL);
602
603 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
604
605 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
606 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
607 GSWIP_PCE_TBL_CTRL_GMAP_MASK);
608 if (tbl->type)
609 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
610 if (tbl->valid)
611 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
612 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
613 crtl |= GSWIP_PCE_TBL_CTRL_BAS;
614 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
615
616 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
617 GSWIP_PCE_TBL_CTRL_BAS);
618
619 mutex_unlock(&priv->pce_table_lock);
620
621 return err;
622 }
623
624 /* Add the LAN port into a bridge with the CPU port by
625 * default. This prevents automatic forwarding of
626 * packages between the LAN ports when no explicit
627 * bridge is configured.
628 */
gswip_add_single_port_br(struct gswip_priv * priv,int port,bool add)629 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
630 {
631 struct gswip_pce_table_entry vlan_active = {0,};
632 struct gswip_pce_table_entry vlan_mapping = {0,};
633 unsigned int cpu_port = priv->hw_info->cpu_port;
634 unsigned int max_ports = priv->hw_info->max_ports;
635 int err;
636
637 if (port >= max_ports) {
638 dev_err(priv->dev, "single port for %i supported\n", port);
639 return -EIO;
640 }
641
642 vlan_active.index = port + 1;
643 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
644 vlan_active.key[0] = 0; /* vid */
645 vlan_active.val[0] = port + 1 /* fid */;
646 vlan_active.valid = add;
647 err = gswip_pce_table_entry_write(priv, &vlan_active);
648 if (err) {
649 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
650 return err;
651 }
652
653 if (!add)
654 return 0;
655
656 vlan_mapping.index = port + 1;
657 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
658 vlan_mapping.val[0] = 0 /* vid */;
659 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
660 vlan_mapping.val[2] = 0;
661 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
662 if (err) {
663 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
664 return err;
665 }
666
667 return 0;
668 }
669
gswip_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)670 static int gswip_port_enable(struct dsa_switch *ds, int port,
671 struct phy_device *phydev)
672 {
673 struct gswip_priv *priv = ds->priv;
674 int err;
675
676 if (!dsa_is_user_port(ds, port))
677 return 0;
678
679 if (!dsa_is_cpu_port(ds, port)) {
680 err = gswip_add_single_port_br(priv, port, true);
681 if (err)
682 return err;
683 }
684
685 /* RMON Counter Enable for port */
686 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
687
688 /* enable port fetch/store dma & VLAN Modification */
689 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
690 GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
691 GSWIP_FDMA_PCTRLp(port));
692 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
693 GSWIP_SDMA_PCTRLp(port));
694
695 if (!dsa_is_cpu_port(ds, port)) {
696 u32 mdio_phy = 0;
697
698 if (phydev)
699 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
700
701 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
702 GSWIP_MDIO_PHYp(port));
703 }
704
705 return 0;
706 }
707
gswip_port_disable(struct dsa_switch * ds,int port)708 static void gswip_port_disable(struct dsa_switch *ds, int port)
709 {
710 struct gswip_priv *priv = ds->priv;
711
712 if (!dsa_is_user_port(ds, port))
713 return;
714
715 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
716 GSWIP_FDMA_PCTRLp(port));
717 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
718 GSWIP_SDMA_PCTRLp(port));
719 }
720
gswip_pce_load_microcode(struct gswip_priv * priv)721 static int gswip_pce_load_microcode(struct gswip_priv *priv)
722 {
723 int i;
724 int err;
725
726 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
727 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
728 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
729 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
730
731 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
732 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
733 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
734 GSWIP_PCE_TBL_VAL(0));
735 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
736 GSWIP_PCE_TBL_VAL(1));
737 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
738 GSWIP_PCE_TBL_VAL(2));
739 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
740 GSWIP_PCE_TBL_VAL(3));
741
742 /* start the table access: */
743 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
744 GSWIP_PCE_TBL_CTRL);
745 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
746 GSWIP_PCE_TBL_CTRL_BAS);
747 if (err)
748 return err;
749 }
750
751 /* tell the switch that the microcode is loaded */
752 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
753 GSWIP_PCE_GCTRL_0);
754
755 return 0;
756 }
757
gswip_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)758 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
759 bool vlan_filtering,
760 struct netlink_ext_ack *extack)
761 {
762 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
763 struct gswip_priv *priv = ds->priv;
764
765 /* Do not allow changing the VLAN filtering options while in bridge */
766 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) {
767 NL_SET_ERR_MSG_MOD(extack,
768 "Dynamic toggling of vlan_filtering not supported");
769 return -EIO;
770 }
771
772 if (vlan_filtering) {
773 /* Use port based VLAN tag */
774 gswip_switch_mask(priv,
775 GSWIP_PCE_VCTRL_VSR,
776 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
777 GSWIP_PCE_VCTRL_VEMR,
778 GSWIP_PCE_VCTRL(port));
779 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
780 GSWIP_PCE_PCTRL_0p(port));
781 } else {
782 /* Use port based VLAN tag */
783 gswip_switch_mask(priv,
784 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
785 GSWIP_PCE_VCTRL_VEMR,
786 GSWIP_PCE_VCTRL_VSR,
787 GSWIP_PCE_VCTRL(port));
788 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
789 GSWIP_PCE_PCTRL_0p(port));
790 }
791
792 return 0;
793 }
794
gswip_setup(struct dsa_switch * ds)795 static int gswip_setup(struct dsa_switch *ds)
796 {
797 struct gswip_priv *priv = ds->priv;
798 unsigned int cpu_port = priv->hw_info->cpu_port;
799 int i;
800 int err;
801
802 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
803 usleep_range(5000, 10000);
804 gswip_switch_w(priv, 0, GSWIP_SWRES);
805
806 /* disable port fetch/store dma on all ports */
807 for (i = 0; i < priv->hw_info->max_ports; i++) {
808 gswip_port_disable(ds, i);
809 gswip_port_vlan_filtering(ds, i, false, NULL);
810 }
811
812 /* enable Switch */
813 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
814
815 err = gswip_pce_load_microcode(priv);
816 if (err) {
817 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
818 return err;
819 }
820
821 /* Default unknown Broadcast/Multicast/Unicast port maps */
822 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
823 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
824 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
825
826 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
827 * interoperability problem with this auto polling mechanism because
828 * their status registers think that the link is in a different state
829 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set
830 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the
831 * auto polling state machine consider the link being negotiated with
832 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads
833 * to the switch port being completely dead (RX and TX are both not
834 * working).
835 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F
836 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes
837 * it would work fine for a few minutes to hours and then stop, on
838 * other device it would no traffic could be sent or received at all.
839 * Testing shows that when PHY auto polling is disabled these problems
840 * go away.
841 */
842 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
843
844 /* Configure the MDIO Clock 2.5 MHz */
845 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
846
847 /* Disable the xMII interface and clear it's isolation bit */
848 for (i = 0; i < priv->hw_info->max_ports; i++)
849 gswip_mii_mask_cfg(priv,
850 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
851 0, i);
852
853 /* enable special tag insertion on cpu port */
854 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
855 GSWIP_FDMA_PCTRLp(cpu_port));
856
857 /* accept special tag in ingress direction */
858 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
859 GSWIP_PCE_PCTRL_0p(cpu_port));
860
861 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
862 GSWIP_MAC_CTRL_2p(cpu_port));
863 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN,
864 GSWIP_MAC_FLEN);
865 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
866 GSWIP_BM_QUEUE_GCTRL);
867
868 /* VLAN aware Switching */
869 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
870
871 /* Flush MAC Table */
872 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
873
874 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
875 GSWIP_PCE_GCTRL_0_MTFL);
876 if (err) {
877 dev_err(priv->dev, "MAC flushing didn't finish\n");
878 return err;
879 }
880
881 gswip_port_enable(ds, cpu_port, NULL);
882
883 ds->configure_vlan_while_not_filtering = false;
884
885 return 0;
886 }
887
gswip_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)888 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
889 int port,
890 enum dsa_tag_protocol mp)
891 {
892 return DSA_TAG_PROTO_GSWIP;
893 }
894
gswip_vlan_active_create(struct gswip_priv * priv,struct net_device * bridge,int fid,u16 vid)895 static int gswip_vlan_active_create(struct gswip_priv *priv,
896 struct net_device *bridge,
897 int fid, u16 vid)
898 {
899 struct gswip_pce_table_entry vlan_active = {0,};
900 unsigned int max_ports = priv->hw_info->max_ports;
901 int idx = -1;
902 int err;
903 int i;
904
905 /* Look for a free slot */
906 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
907 if (!priv->vlans[i].bridge) {
908 idx = i;
909 break;
910 }
911 }
912
913 if (idx == -1)
914 return -ENOSPC;
915
916 if (fid == -1)
917 fid = idx;
918
919 vlan_active.index = idx;
920 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
921 vlan_active.key[0] = vid;
922 vlan_active.val[0] = fid;
923 vlan_active.valid = true;
924
925 err = gswip_pce_table_entry_write(priv, &vlan_active);
926 if (err) {
927 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
928 return err;
929 }
930
931 priv->vlans[idx].bridge = bridge;
932 priv->vlans[idx].vid = vid;
933 priv->vlans[idx].fid = fid;
934
935 return idx;
936 }
937
gswip_vlan_active_remove(struct gswip_priv * priv,int idx)938 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
939 {
940 struct gswip_pce_table_entry vlan_active = {0,};
941 int err;
942
943 vlan_active.index = idx;
944 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
945 vlan_active.valid = false;
946 err = gswip_pce_table_entry_write(priv, &vlan_active);
947 if (err)
948 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
949 priv->vlans[idx].bridge = NULL;
950
951 return err;
952 }
953
gswip_vlan_add_unaware(struct gswip_priv * priv,struct net_device * bridge,int port)954 static int gswip_vlan_add_unaware(struct gswip_priv *priv,
955 struct net_device *bridge, int port)
956 {
957 struct gswip_pce_table_entry vlan_mapping = {0,};
958 unsigned int max_ports = priv->hw_info->max_ports;
959 unsigned int cpu_port = priv->hw_info->cpu_port;
960 bool active_vlan_created = false;
961 int idx = -1;
962 int i;
963 int err;
964
965 /* Check if there is already a page for this bridge */
966 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
967 if (priv->vlans[i].bridge == bridge) {
968 idx = i;
969 break;
970 }
971 }
972
973 /* If this bridge is not programmed yet, add a Active VLAN table
974 * entry in a free slot and prepare the VLAN mapping table entry.
975 */
976 if (idx == -1) {
977 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
978 if (idx < 0)
979 return idx;
980 active_vlan_created = true;
981
982 vlan_mapping.index = idx;
983 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
984 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
985 vlan_mapping.val[0] = 0;
986 } else {
987 /* Read the existing VLAN mapping entry from the switch */
988 vlan_mapping.index = idx;
989 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
990 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
991 if (err) {
992 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
993 err);
994 return err;
995 }
996 }
997
998 /* Update the VLAN mapping entry and write it to the switch */
999 vlan_mapping.val[1] |= BIT(cpu_port);
1000 vlan_mapping.val[1] |= BIT(port);
1001 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1002 if (err) {
1003 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1004 /* In case an Active VLAN was creaetd delete it again */
1005 if (active_vlan_created)
1006 gswip_vlan_active_remove(priv, idx);
1007 return err;
1008 }
1009
1010 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1011 return 0;
1012 }
1013
gswip_vlan_add_aware(struct gswip_priv * priv,struct net_device * bridge,int port,u16 vid,bool untagged,bool pvid)1014 static int gswip_vlan_add_aware(struct gswip_priv *priv,
1015 struct net_device *bridge, int port,
1016 u16 vid, bool untagged,
1017 bool pvid)
1018 {
1019 struct gswip_pce_table_entry vlan_mapping = {0,};
1020 unsigned int max_ports = priv->hw_info->max_ports;
1021 unsigned int cpu_port = priv->hw_info->cpu_port;
1022 bool active_vlan_created = false;
1023 int idx = -1;
1024 int fid = -1;
1025 int i;
1026 int err;
1027
1028 /* Check if there is already a page for this bridge */
1029 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1030 if (priv->vlans[i].bridge == bridge) {
1031 if (fid != -1 && fid != priv->vlans[i].fid)
1032 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1033 fid = priv->vlans[i].fid;
1034 if (priv->vlans[i].vid == vid) {
1035 idx = i;
1036 break;
1037 }
1038 }
1039 }
1040
1041 /* If this bridge is not programmed yet, add a Active VLAN table
1042 * entry in a free slot and prepare the VLAN mapping table entry.
1043 */
1044 if (idx == -1) {
1045 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1046 if (idx < 0)
1047 return idx;
1048 active_vlan_created = true;
1049
1050 vlan_mapping.index = idx;
1051 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1052 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1053 vlan_mapping.val[0] = vid;
1054 } else {
1055 /* Read the existing VLAN mapping entry from the switch */
1056 vlan_mapping.index = idx;
1057 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1058 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1059 if (err) {
1060 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1061 err);
1062 return err;
1063 }
1064 }
1065
1066 vlan_mapping.val[0] = vid;
1067 /* Update the VLAN mapping entry and write it to the switch */
1068 vlan_mapping.val[1] |= BIT(cpu_port);
1069 vlan_mapping.val[2] |= BIT(cpu_port);
1070 vlan_mapping.val[1] |= BIT(port);
1071 if (untagged)
1072 vlan_mapping.val[2] &= ~BIT(port);
1073 else
1074 vlan_mapping.val[2] |= BIT(port);
1075 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1076 if (err) {
1077 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1078 /* In case an Active VLAN was creaetd delete it again */
1079 if (active_vlan_created)
1080 gswip_vlan_active_remove(priv, idx);
1081 return err;
1082 }
1083
1084 if (pvid)
1085 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1086
1087 return 0;
1088 }
1089
gswip_vlan_remove(struct gswip_priv * priv,struct net_device * bridge,int port,u16 vid,bool pvid,bool vlan_aware)1090 static int gswip_vlan_remove(struct gswip_priv *priv,
1091 struct net_device *bridge, int port,
1092 u16 vid, bool pvid, bool vlan_aware)
1093 {
1094 struct gswip_pce_table_entry vlan_mapping = {0,};
1095 unsigned int max_ports = priv->hw_info->max_ports;
1096 unsigned int cpu_port = priv->hw_info->cpu_port;
1097 int idx = -1;
1098 int i;
1099 int err;
1100
1101 /* Check if there is already a page for this bridge */
1102 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1103 if (priv->vlans[i].bridge == bridge &&
1104 (!vlan_aware || priv->vlans[i].vid == vid)) {
1105 idx = i;
1106 break;
1107 }
1108 }
1109
1110 if (idx == -1) {
1111 dev_err(priv->dev, "bridge to leave does not exists\n");
1112 return -ENOENT;
1113 }
1114
1115 vlan_mapping.index = idx;
1116 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1117 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1118 if (err) {
1119 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1120 return err;
1121 }
1122
1123 vlan_mapping.val[1] &= ~BIT(port);
1124 vlan_mapping.val[2] &= ~BIT(port);
1125 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1126 if (err) {
1127 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1128 return err;
1129 }
1130
1131 /* In case all ports are removed from the bridge, remove the VLAN */
1132 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1133 err = gswip_vlan_active_remove(priv, idx);
1134 if (err) {
1135 dev_err(priv->dev, "failed to write active VLAN: %d\n",
1136 err);
1137 return err;
1138 }
1139 }
1140
1141 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1142 if (pvid)
1143 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1144
1145 return 0;
1146 }
1147
gswip_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * bridge)1148 static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1149 struct net_device *bridge)
1150 {
1151 struct gswip_priv *priv = ds->priv;
1152 int err;
1153
1154 /* When the bridge uses VLAN filtering we have to configure VLAN
1155 * specific bridges. No bridge is configured here.
1156 */
1157 if (!br_vlan_enabled(bridge)) {
1158 err = gswip_vlan_add_unaware(priv, bridge, port);
1159 if (err)
1160 return err;
1161 priv->port_vlan_filter &= ~BIT(port);
1162 } else {
1163 priv->port_vlan_filter |= BIT(port);
1164 }
1165 return gswip_add_single_port_br(priv, port, false);
1166 }
1167
gswip_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * bridge)1168 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1169 struct net_device *bridge)
1170 {
1171 struct gswip_priv *priv = ds->priv;
1172
1173 gswip_add_single_port_br(priv, port, true);
1174
1175 /* When the bridge uses VLAN filtering we have to configure VLAN
1176 * specific bridges. No bridge is configured here.
1177 */
1178 if (!br_vlan_enabled(bridge))
1179 gswip_vlan_remove(priv, bridge, port, 0, true, false);
1180 }
1181
gswip_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1182 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1183 const struct switchdev_obj_port_vlan *vlan,
1184 struct netlink_ext_ack *extack)
1185 {
1186 struct gswip_priv *priv = ds->priv;
1187 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1188 unsigned int max_ports = priv->hw_info->max_ports;
1189 int pos = max_ports;
1190 int i, idx = -1;
1191
1192 /* We only support VLAN filtering on bridges */
1193 if (!dsa_is_cpu_port(ds, port) && !bridge)
1194 return -EOPNOTSUPP;
1195
1196 /* Check if there is already a page for this VLAN */
1197 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1198 if (priv->vlans[i].bridge == bridge &&
1199 priv->vlans[i].vid == vlan->vid) {
1200 idx = i;
1201 break;
1202 }
1203 }
1204
1205 /* If this VLAN is not programmed yet, we have to reserve
1206 * one entry in the VLAN table. Make sure we start at the
1207 * next position round.
1208 */
1209 if (idx == -1) {
1210 /* Look for a free slot */
1211 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1212 if (!priv->vlans[pos].bridge) {
1213 idx = pos;
1214 pos++;
1215 break;
1216 }
1217 }
1218
1219 if (idx == -1) {
1220 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table");
1221 return -ENOSPC;
1222 }
1223 }
1224
1225 return 0;
1226 }
1227
gswip_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1228 static int gswip_port_vlan_add(struct dsa_switch *ds, int port,
1229 const struct switchdev_obj_port_vlan *vlan,
1230 struct netlink_ext_ack *extack)
1231 {
1232 struct gswip_priv *priv = ds->priv;
1233 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1234 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1235 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1236 int err;
1237
1238 err = gswip_port_vlan_prepare(ds, port, vlan, extack);
1239 if (err)
1240 return err;
1241
1242 /* We have to receive all packets on the CPU port and should not
1243 * do any VLAN filtering here. This is also called with bridge
1244 * NULL and then we do not know for which bridge to configure
1245 * this.
1246 */
1247 if (dsa_is_cpu_port(ds, port))
1248 return 0;
1249
1250 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid,
1251 untagged, pvid);
1252 }
1253
gswip_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1254 static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1255 const struct switchdev_obj_port_vlan *vlan)
1256 {
1257 struct gswip_priv *priv = ds->priv;
1258 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1259 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1260
1261 /* We have to receive all packets on the CPU port and should not
1262 * do any VLAN filtering here. This is also called with bridge
1263 * NULL and then we do not know for which bridge to configure
1264 * this.
1265 */
1266 if (dsa_is_cpu_port(ds, port))
1267 return 0;
1268
1269 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true);
1270 }
1271
gswip_port_fast_age(struct dsa_switch * ds,int port)1272 static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1273 {
1274 struct gswip_priv *priv = ds->priv;
1275 struct gswip_pce_table_entry mac_bridge = {0,};
1276 int i;
1277 int err;
1278
1279 for (i = 0; i < 2048; i++) {
1280 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1281 mac_bridge.index = i;
1282
1283 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1284 if (err) {
1285 dev_err(priv->dev, "failed to read mac bridge: %d\n",
1286 err);
1287 return;
1288 }
1289
1290 if (!mac_bridge.valid)
1291 continue;
1292
1293 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1294 continue;
1295
1296 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1297 continue;
1298
1299 mac_bridge.valid = false;
1300 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1301 if (err) {
1302 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1303 err);
1304 return;
1305 }
1306 }
1307 }
1308
gswip_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1309 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1310 {
1311 struct gswip_priv *priv = ds->priv;
1312 u32 stp_state;
1313
1314 switch (state) {
1315 case BR_STATE_DISABLED:
1316 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1317 GSWIP_SDMA_PCTRLp(port));
1318 return;
1319 case BR_STATE_BLOCKING:
1320 case BR_STATE_LISTENING:
1321 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1322 break;
1323 case BR_STATE_LEARNING:
1324 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1325 break;
1326 case BR_STATE_FORWARDING:
1327 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1328 break;
1329 default:
1330 dev_err(priv->dev, "invalid STP state: %d\n", state);
1331 return;
1332 }
1333
1334 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1335 GSWIP_SDMA_PCTRLp(port));
1336 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1337 GSWIP_PCE_PCTRL_0p(port));
1338 }
1339
gswip_port_fdb(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,bool add)1340 static int gswip_port_fdb(struct dsa_switch *ds, int port,
1341 const unsigned char *addr, u16 vid, bool add)
1342 {
1343 struct gswip_priv *priv = ds->priv;
1344 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1345 struct gswip_pce_table_entry mac_bridge = {0,};
1346 unsigned int cpu_port = priv->hw_info->cpu_port;
1347 int fid = -1;
1348 int i;
1349 int err;
1350
1351 if (!bridge)
1352 return -EINVAL;
1353
1354 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1355 if (priv->vlans[i].bridge == bridge) {
1356 fid = priv->vlans[i].fid;
1357 break;
1358 }
1359 }
1360
1361 if (fid == -1) {
1362 dev_err(priv->dev, "Port not part of a bridge\n");
1363 return -EINVAL;
1364 }
1365
1366 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1367 mac_bridge.key_mode = true;
1368 mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1369 mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1370 mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1371 mac_bridge.key[3] = fid;
1372 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1373 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1374 mac_bridge.valid = add;
1375
1376 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1377 if (err)
1378 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
1379
1380 return err;
1381 }
1382
gswip_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)1383 static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1384 const unsigned char *addr, u16 vid)
1385 {
1386 return gswip_port_fdb(ds, port, addr, vid, true);
1387 }
1388
gswip_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)1389 static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1390 const unsigned char *addr, u16 vid)
1391 {
1392 return gswip_port_fdb(ds, port, addr, vid, false);
1393 }
1394
gswip_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1395 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1396 dsa_fdb_dump_cb_t *cb, void *data)
1397 {
1398 struct gswip_priv *priv = ds->priv;
1399 struct gswip_pce_table_entry mac_bridge = {0,};
1400 unsigned char addr[6];
1401 int i;
1402 int err;
1403
1404 for (i = 0; i < 2048; i++) {
1405 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1406 mac_bridge.index = i;
1407
1408 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1409 if (err) {
1410 dev_err(priv->dev, "failed to write mac bridge: %d\n",
1411 err);
1412 return err;
1413 }
1414
1415 if (!mac_bridge.valid)
1416 continue;
1417
1418 addr[5] = mac_bridge.key[0] & 0xff;
1419 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1420 addr[3] = mac_bridge.key[1] & 0xff;
1421 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1422 addr[1] = mac_bridge.key[2] & 0xff;
1423 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1424 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1425 if (mac_bridge.val[0] & BIT(port)) {
1426 err = cb(addr, 0, true, data);
1427 if (err)
1428 return err;
1429 }
1430 } else {
1431 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
1432 err = cb(addr, 0, false, data);
1433 if (err)
1434 return err;
1435 }
1436 }
1437 }
1438 return 0;
1439 }
1440
gswip_phylink_set_capab(unsigned long * supported,struct phylink_link_state * state)1441 static void gswip_phylink_set_capab(unsigned long *supported,
1442 struct phylink_link_state *state)
1443 {
1444 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1445
1446 /* Allow all the expected bits */
1447 phylink_set(mask, Autoneg);
1448 phylink_set_port_modes(mask);
1449 phylink_set(mask, Pause);
1450 phylink_set(mask, Asym_Pause);
1451
1452 /* With the exclusion of MII, Reverse MII and Reduced MII, we
1453 * support Gigabit, including Half duplex
1454 */
1455 if (state->interface != PHY_INTERFACE_MODE_MII &&
1456 state->interface != PHY_INTERFACE_MODE_REVMII &&
1457 state->interface != PHY_INTERFACE_MODE_RMII) {
1458 phylink_set(mask, 1000baseT_Full);
1459 phylink_set(mask, 1000baseT_Half);
1460 }
1461
1462 phylink_set(mask, 10baseT_Half);
1463 phylink_set(mask, 10baseT_Full);
1464 phylink_set(mask, 100baseT_Half);
1465 phylink_set(mask, 100baseT_Full);
1466
1467 linkmode_and(supported, supported, mask);
1468 linkmode_and(state->advertising, state->advertising, mask);
1469 }
1470
gswip_xrx200_phylink_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)1471 static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port,
1472 unsigned long *supported,
1473 struct phylink_link_state *state)
1474 {
1475 switch (port) {
1476 case 0:
1477 case 1:
1478 if (!phy_interface_mode_is_rgmii(state->interface) &&
1479 state->interface != PHY_INTERFACE_MODE_MII &&
1480 state->interface != PHY_INTERFACE_MODE_REVMII &&
1481 state->interface != PHY_INTERFACE_MODE_RMII)
1482 goto unsupported;
1483 break;
1484 case 2:
1485 case 3:
1486 case 4:
1487 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1488 goto unsupported;
1489 break;
1490 case 5:
1491 if (!phy_interface_mode_is_rgmii(state->interface) &&
1492 state->interface != PHY_INTERFACE_MODE_INTERNAL)
1493 goto unsupported;
1494 break;
1495 default:
1496 linkmode_zero(supported);
1497 dev_err(ds->dev, "Unsupported port: %i\n", port);
1498 return;
1499 }
1500
1501 gswip_phylink_set_capab(supported, state);
1502
1503 return;
1504
1505 unsupported:
1506 linkmode_zero(supported);
1507 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1508 phy_modes(state->interface), port);
1509 }
1510
gswip_xrx300_phylink_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)1511 static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port,
1512 unsigned long *supported,
1513 struct phylink_link_state *state)
1514 {
1515 switch (port) {
1516 case 0:
1517 if (!phy_interface_mode_is_rgmii(state->interface) &&
1518 state->interface != PHY_INTERFACE_MODE_GMII &&
1519 state->interface != PHY_INTERFACE_MODE_RMII)
1520 goto unsupported;
1521 break;
1522 case 1:
1523 case 2:
1524 case 3:
1525 case 4:
1526 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1527 goto unsupported;
1528 break;
1529 case 5:
1530 if (!phy_interface_mode_is_rgmii(state->interface) &&
1531 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1532 state->interface != PHY_INTERFACE_MODE_RMII)
1533 goto unsupported;
1534 break;
1535 default:
1536 linkmode_zero(supported);
1537 dev_err(ds->dev, "Unsupported port: %i\n", port);
1538 return;
1539 }
1540
1541 gswip_phylink_set_capab(supported, state);
1542
1543 return;
1544
1545 unsupported:
1546 linkmode_zero(supported);
1547 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1548 phy_modes(state->interface), port);
1549 }
1550
gswip_port_set_link(struct gswip_priv * priv,int port,bool link)1551 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1552 {
1553 u32 mdio_phy;
1554
1555 if (link)
1556 mdio_phy = GSWIP_MDIO_PHY_LINK_UP;
1557 else
1558 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
1559
1560 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
1561 GSWIP_MDIO_PHYp(port));
1562 }
1563
gswip_port_set_speed(struct gswip_priv * priv,int port,int speed,phy_interface_t interface)1564 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
1565 phy_interface_t interface)
1566 {
1567 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0;
1568
1569 switch (speed) {
1570 case SPEED_10:
1571 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10;
1572
1573 if (interface == PHY_INTERFACE_MODE_RMII)
1574 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1575 else
1576 mii_cfg = GSWIP_MII_CFG_RATE_M2P5;
1577
1578 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1579 break;
1580
1581 case SPEED_100:
1582 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100;
1583
1584 if (interface == PHY_INTERFACE_MODE_RMII)
1585 mii_cfg = GSWIP_MII_CFG_RATE_M50;
1586 else
1587 mii_cfg = GSWIP_MII_CFG_RATE_M25;
1588
1589 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII;
1590 break;
1591
1592 case SPEED_1000:
1593 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
1594
1595 mii_cfg = GSWIP_MII_CFG_RATE_M125;
1596
1597 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII;
1598 break;
1599 }
1600
1601 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
1602 GSWIP_MDIO_PHYp(port));
1603 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
1604 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
1605 GSWIP_MAC_CTRL_0p(port));
1606 }
1607
gswip_port_set_duplex(struct gswip_priv * priv,int port,int duplex)1608 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
1609 {
1610 u32 mac_ctrl_0, mdio_phy;
1611
1612 if (duplex == DUPLEX_FULL) {
1613 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN;
1614 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN;
1615 } else {
1616 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS;
1617 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
1618 }
1619
1620 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
1621 GSWIP_MAC_CTRL_0p(port));
1622 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
1623 GSWIP_MDIO_PHYp(port));
1624 }
1625
gswip_port_set_pause(struct gswip_priv * priv,int port,bool tx_pause,bool rx_pause)1626 static void gswip_port_set_pause(struct gswip_priv *priv, int port,
1627 bool tx_pause, bool rx_pause)
1628 {
1629 u32 mac_ctrl_0, mdio_phy;
1630
1631 if (tx_pause && rx_pause) {
1632 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX;
1633 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1634 GSWIP_MDIO_PHY_FCONRX_EN;
1635 } else if (tx_pause) {
1636 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX;
1637 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN |
1638 GSWIP_MDIO_PHY_FCONRX_DIS;
1639 } else if (rx_pause) {
1640 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX;
1641 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1642 GSWIP_MDIO_PHY_FCONRX_EN;
1643 } else {
1644 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE;
1645 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS |
1646 GSWIP_MDIO_PHY_FCONRX_DIS;
1647 }
1648
1649 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
1650 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
1651 gswip_mdio_mask(priv,
1652 GSWIP_MDIO_PHY_FCONTX_MASK |
1653 GSWIP_MDIO_PHY_FCONRX_MASK,
1654 mdio_phy, GSWIP_MDIO_PHYp(port));
1655 }
1656
gswip_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)1657 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1658 unsigned int mode,
1659 const struct phylink_link_state *state)
1660 {
1661 struct gswip_priv *priv = ds->priv;
1662 u32 miicfg = 0;
1663
1664 miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1665
1666 switch (state->interface) {
1667 case PHY_INTERFACE_MODE_MII:
1668 case PHY_INTERFACE_MODE_INTERNAL:
1669 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1670 break;
1671 case PHY_INTERFACE_MODE_REVMII:
1672 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1673 break;
1674 case PHY_INTERFACE_MODE_RMII:
1675 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1676
1677 /* Configure the RMII clock as output: */
1678 miicfg |= GSWIP_MII_CFG_RMII_CLK;
1679 break;
1680 case PHY_INTERFACE_MODE_RGMII:
1681 case PHY_INTERFACE_MODE_RGMII_ID:
1682 case PHY_INTERFACE_MODE_RGMII_RXID:
1683 case PHY_INTERFACE_MODE_RGMII_TXID:
1684 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1685 break;
1686 case PHY_INTERFACE_MODE_GMII:
1687 miicfg |= GSWIP_MII_CFG_MODE_GMII;
1688 break;
1689 default:
1690 dev_err(ds->dev,
1691 "Unsupported interface: %d\n", state->interface);
1692 return;
1693 }
1694
1695 gswip_mii_mask_cfg(priv,
1696 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK |
1697 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS,
1698 miicfg, port);
1699
1700 switch (state->interface) {
1701 case PHY_INTERFACE_MODE_RGMII_ID:
1702 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1703 GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1704 break;
1705 case PHY_INTERFACE_MODE_RGMII_RXID:
1706 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1707 break;
1708 case PHY_INTERFACE_MODE_RGMII_TXID:
1709 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1710 break;
1711 default:
1712 break;
1713 }
1714 }
1715
gswip_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1716 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1717 unsigned int mode,
1718 phy_interface_t interface)
1719 {
1720 struct gswip_priv *priv = ds->priv;
1721
1722 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1723
1724 if (!dsa_is_cpu_port(ds, port))
1725 gswip_port_set_link(priv, port, false);
1726 }
1727
gswip_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1728 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1729 unsigned int mode,
1730 phy_interface_t interface,
1731 struct phy_device *phydev,
1732 int speed, int duplex,
1733 bool tx_pause, bool rx_pause)
1734 {
1735 struct gswip_priv *priv = ds->priv;
1736
1737 if (!dsa_is_cpu_port(ds, port)) {
1738 gswip_port_set_link(priv, port, true);
1739 gswip_port_set_speed(priv, port, speed, interface);
1740 gswip_port_set_duplex(priv, port, duplex);
1741 gswip_port_set_pause(priv, port, tx_pause, rx_pause);
1742 }
1743
1744 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1745 }
1746
gswip_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1747 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1748 uint8_t *data)
1749 {
1750 int i;
1751
1752 if (stringset != ETH_SS_STATS)
1753 return;
1754
1755 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1756 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1757 ETH_GSTRING_LEN);
1758 }
1759
gswip_bcm_ram_entry_read(struct gswip_priv * priv,u32 table,u32 index)1760 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1761 u32 index)
1762 {
1763 u32 result;
1764 int err;
1765
1766 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1767 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1768 GSWIP_BM_RAM_CTRL_OPMOD,
1769 table | GSWIP_BM_RAM_CTRL_BAS,
1770 GSWIP_BM_RAM_CTRL);
1771
1772 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1773 GSWIP_BM_RAM_CTRL_BAS);
1774 if (err) {
1775 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1776 table, index);
1777 return 0;
1778 }
1779
1780 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1781 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1782
1783 return result;
1784 }
1785
gswip_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1786 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1787 uint64_t *data)
1788 {
1789 struct gswip_priv *priv = ds->priv;
1790 const struct gswip_rmon_cnt_desc *rmon_cnt;
1791 int i;
1792 u64 high;
1793
1794 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1795 rmon_cnt = &gswip_rmon_cnt[i];
1796
1797 data[i] = gswip_bcm_ram_entry_read(priv, port,
1798 rmon_cnt->offset);
1799 if (rmon_cnt->size == 2) {
1800 high = gswip_bcm_ram_entry_read(priv, port,
1801 rmon_cnt->offset + 1);
1802 data[i] |= high << 32;
1803 }
1804 }
1805 }
1806
gswip_get_sset_count(struct dsa_switch * ds,int port,int sset)1807 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1808 {
1809 if (sset != ETH_SS_STATS)
1810 return 0;
1811
1812 return ARRAY_SIZE(gswip_rmon_cnt);
1813 }
1814
1815 static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
1816 .get_tag_protocol = gswip_get_tag_protocol,
1817 .setup = gswip_setup,
1818 .port_enable = gswip_port_enable,
1819 .port_disable = gswip_port_disable,
1820 .port_bridge_join = gswip_port_bridge_join,
1821 .port_bridge_leave = gswip_port_bridge_leave,
1822 .port_fast_age = gswip_port_fast_age,
1823 .port_vlan_filtering = gswip_port_vlan_filtering,
1824 .port_vlan_add = gswip_port_vlan_add,
1825 .port_vlan_del = gswip_port_vlan_del,
1826 .port_stp_state_set = gswip_port_stp_state_set,
1827 .port_fdb_add = gswip_port_fdb_add,
1828 .port_fdb_del = gswip_port_fdb_del,
1829 .port_fdb_dump = gswip_port_fdb_dump,
1830 .phylink_validate = gswip_xrx200_phylink_validate,
1831 .phylink_mac_config = gswip_phylink_mac_config,
1832 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1833 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1834 .get_strings = gswip_get_strings,
1835 .get_ethtool_stats = gswip_get_ethtool_stats,
1836 .get_sset_count = gswip_get_sset_count,
1837 };
1838
1839 static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
1840 .get_tag_protocol = gswip_get_tag_protocol,
1841 .setup = gswip_setup,
1842 .port_enable = gswip_port_enable,
1843 .port_disable = gswip_port_disable,
1844 .port_bridge_join = gswip_port_bridge_join,
1845 .port_bridge_leave = gswip_port_bridge_leave,
1846 .port_fast_age = gswip_port_fast_age,
1847 .port_vlan_filtering = gswip_port_vlan_filtering,
1848 .port_vlan_add = gswip_port_vlan_add,
1849 .port_vlan_del = gswip_port_vlan_del,
1850 .port_stp_state_set = gswip_port_stp_state_set,
1851 .port_fdb_add = gswip_port_fdb_add,
1852 .port_fdb_del = gswip_port_fdb_del,
1853 .port_fdb_dump = gswip_port_fdb_dump,
1854 .phylink_validate = gswip_xrx300_phylink_validate,
1855 .phylink_mac_config = gswip_phylink_mac_config,
1856 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1857 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1858 .get_strings = gswip_get_strings,
1859 .get_ethtool_stats = gswip_get_ethtool_stats,
1860 .get_sset_count = gswip_get_sset_count,
1861 };
1862
1863 static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1864 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1865 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1866 };
1867
1868 static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1869 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1870 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1871 };
1872
1873 static const struct xway_gphy_match_data xrx300_gphy_data = {
1874 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1875 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1876 };
1877
1878 static const struct of_device_id xway_gphy_match[] = {
1879 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1880 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1881 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1882 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1883 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1884 {},
1885 };
1886
gswip_gphy_fw_load(struct gswip_priv * priv,struct gswip_gphy_fw * gphy_fw)1887 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1888 {
1889 struct device *dev = priv->dev;
1890 const struct firmware *fw;
1891 void *fw_addr;
1892 dma_addr_t dma_addr;
1893 dma_addr_t dev_addr;
1894 size_t size;
1895 int ret;
1896
1897 ret = clk_prepare_enable(gphy_fw->clk_gate);
1898 if (ret)
1899 return ret;
1900
1901 reset_control_assert(gphy_fw->reset);
1902
1903 /* The vendor BSP uses a 200ms delay after asserting the reset line.
1904 * Without this some users are observing that the PHY is not coming up
1905 * on the MDIO bus.
1906 */
1907 msleep(200);
1908
1909 ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1910 if (ret) {
1911 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1912 gphy_fw->fw_name, ret);
1913 return ret;
1914 }
1915
1916 /* GPHY cores need the firmware code in a persistent and contiguous
1917 * memory area with a 16 kB boundary aligned start address.
1918 */
1919 size = fw->size + XRX200_GPHY_FW_ALIGN;
1920
1921 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1922 if (fw_addr) {
1923 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1924 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1925 memcpy(fw_addr, fw->data, fw->size);
1926 } else {
1927 dev_err(dev, "failed to alloc firmware memory\n");
1928 release_firmware(fw);
1929 return -ENOMEM;
1930 }
1931
1932 release_firmware(fw);
1933
1934 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1935 if (ret)
1936 return ret;
1937
1938 reset_control_deassert(gphy_fw->reset);
1939
1940 return ret;
1941 }
1942
gswip_gphy_fw_probe(struct gswip_priv * priv,struct gswip_gphy_fw * gphy_fw,struct device_node * gphy_fw_np,int i)1943 static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1944 struct gswip_gphy_fw *gphy_fw,
1945 struct device_node *gphy_fw_np, int i)
1946 {
1947 struct device *dev = priv->dev;
1948 u32 gphy_mode;
1949 int ret;
1950 char gphyname[10];
1951
1952 snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1953
1954 gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1955 if (IS_ERR(gphy_fw->clk_gate)) {
1956 dev_err(dev, "Failed to lookup gate clock\n");
1957 return PTR_ERR(gphy_fw->clk_gate);
1958 }
1959
1960 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1961 if (ret)
1962 return ret;
1963
1964 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1965 /* Default to GE mode */
1966 if (ret)
1967 gphy_mode = GPHY_MODE_GE;
1968
1969 switch (gphy_mode) {
1970 case GPHY_MODE_FE:
1971 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1972 break;
1973 case GPHY_MODE_GE:
1974 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1975 break;
1976 default:
1977 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1978 return -EINVAL;
1979 }
1980
1981 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
1982 if (IS_ERR(gphy_fw->reset)) {
1983 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
1984 dev_err(dev, "Failed to lookup gphy reset\n");
1985 return PTR_ERR(gphy_fw->reset);
1986 }
1987
1988 return gswip_gphy_fw_load(priv, gphy_fw);
1989 }
1990
gswip_gphy_fw_remove(struct gswip_priv * priv,struct gswip_gphy_fw * gphy_fw)1991 static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1992 struct gswip_gphy_fw *gphy_fw)
1993 {
1994 int ret;
1995
1996 /* check if the device was fully probed */
1997 if (!gphy_fw->fw_name)
1998 return;
1999
2000 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
2001 if (ret)
2002 dev_err(priv->dev, "can not reset GPHY FW pointer");
2003
2004 clk_disable_unprepare(gphy_fw->clk_gate);
2005
2006 reset_control_put(gphy_fw->reset);
2007 }
2008
gswip_gphy_fw_list(struct gswip_priv * priv,struct device_node * gphy_fw_list_np,u32 version)2009 static int gswip_gphy_fw_list(struct gswip_priv *priv,
2010 struct device_node *gphy_fw_list_np, u32 version)
2011 {
2012 struct device *dev = priv->dev;
2013 struct device_node *gphy_fw_np;
2014 const struct of_device_id *match;
2015 int err;
2016 int i = 0;
2017
2018 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
2019 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
2020 * needs a different GPHY firmware.
2021 */
2022 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
2023 switch (version) {
2024 case GSWIP_VERSION_2_0:
2025 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
2026 break;
2027 case GSWIP_VERSION_2_1:
2028 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
2029 break;
2030 default:
2031 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2032 return -ENOENT;
2033 }
2034 }
2035
2036 match = of_match_node(xway_gphy_match, gphy_fw_list_np);
2037 if (match && match->data)
2038 priv->gphy_fw_name_cfg = match->data;
2039
2040 if (!priv->gphy_fw_name_cfg) {
2041 dev_err(dev, "GPHY compatible type not supported");
2042 return -ENOENT;
2043 }
2044
2045 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
2046 if (!priv->num_gphy_fw)
2047 return -ENOENT;
2048
2049 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
2050 "lantiq,rcu");
2051 if (IS_ERR(priv->rcu_regmap))
2052 return PTR_ERR(priv->rcu_regmap);
2053
2054 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
2055 sizeof(*priv->gphy_fw),
2056 GFP_KERNEL | __GFP_ZERO);
2057 if (!priv->gphy_fw)
2058 return -ENOMEM;
2059
2060 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
2061 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
2062 gphy_fw_np, i);
2063 if (err)
2064 goto remove_gphy;
2065 i++;
2066 }
2067
2068 /* The standalone PHY11G requires 300ms to be fully
2069 * initialized and ready for any MDIO communication after being
2070 * taken out of reset. For the SoC-internal GPHY variant there
2071 * is no (known) documentation for the minimum time after a
2072 * reset. Use the same value as for the standalone variant as
2073 * some users have reported internal PHYs not being detected
2074 * without any delay.
2075 */
2076 msleep(300);
2077
2078 return 0;
2079
2080 remove_gphy:
2081 for (i = 0; i < priv->num_gphy_fw; i++)
2082 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2083 return err;
2084 }
2085
gswip_probe(struct platform_device * pdev)2086 static int gswip_probe(struct platform_device *pdev)
2087 {
2088 struct gswip_priv *priv;
2089 struct device_node *np, *mdio_np, *gphy_fw_np;
2090 struct device *dev = &pdev->dev;
2091 int err;
2092 int i;
2093 u32 version;
2094
2095 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2096 if (!priv)
2097 return -ENOMEM;
2098
2099 priv->gswip = devm_platform_ioremap_resource(pdev, 0);
2100 if (IS_ERR(priv->gswip))
2101 return PTR_ERR(priv->gswip);
2102
2103 priv->mdio = devm_platform_ioremap_resource(pdev, 1);
2104 if (IS_ERR(priv->mdio))
2105 return PTR_ERR(priv->mdio);
2106
2107 priv->mii = devm_platform_ioremap_resource(pdev, 2);
2108 if (IS_ERR(priv->mii))
2109 return PTR_ERR(priv->mii);
2110
2111 priv->hw_info = of_device_get_match_data(dev);
2112 if (!priv->hw_info)
2113 return -EINVAL;
2114
2115 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
2116 if (!priv->ds)
2117 return -ENOMEM;
2118
2119 priv->ds->dev = dev;
2120 priv->ds->num_ports = priv->hw_info->max_ports;
2121 priv->ds->priv = priv;
2122 priv->ds->ops = priv->hw_info->ops;
2123 priv->dev = dev;
2124 mutex_init(&priv->pce_table_lock);
2125 version = gswip_switch_r(priv, GSWIP_VERSION);
2126
2127 np = dev->of_node;
2128 switch (version) {
2129 case GSWIP_VERSION_2_0:
2130 case GSWIP_VERSION_2_1:
2131 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip"))
2132 return -EINVAL;
2133 break;
2134 case GSWIP_VERSION_2_2:
2135 case GSWIP_VERSION_2_2_ETC:
2136 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") &&
2137 !of_device_is_compatible(np, "lantiq,xrx330-gswip"))
2138 return -EINVAL;
2139 break;
2140 default:
2141 dev_err(dev, "unknown GSWIP version: 0x%x", version);
2142 return -ENOENT;
2143 }
2144
2145 /* bring up the mdio bus */
2146 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
2147 if (gphy_fw_np) {
2148 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
2149 of_node_put(gphy_fw_np);
2150 if (err) {
2151 dev_err(dev, "gphy fw probe failed\n");
2152 return err;
2153 }
2154 }
2155
2156 /* bring up the mdio bus */
2157 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
2158 if (mdio_np) {
2159 err = gswip_mdio(priv, mdio_np);
2160 if (err) {
2161 dev_err(dev, "mdio probe failed\n");
2162 goto put_mdio_node;
2163 }
2164 }
2165
2166 err = dsa_register_switch(priv->ds);
2167 if (err) {
2168 dev_err(dev, "dsa switch register failed: %i\n", err);
2169 goto mdio_bus;
2170 }
2171 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
2172 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
2173 priv->hw_info->cpu_port);
2174 err = -EINVAL;
2175 goto disable_switch;
2176 }
2177
2178 platform_set_drvdata(pdev, priv);
2179
2180 dev_info(dev, "probed GSWIP version %lx mod %lx\n",
2181 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
2182 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2183 return 0;
2184
2185 disable_switch:
2186 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2187 dsa_unregister_switch(priv->ds);
2188 mdio_bus:
2189 if (mdio_np)
2190 mdiobus_unregister(priv->ds->slave_mii_bus);
2191 put_mdio_node:
2192 of_node_put(mdio_np);
2193 for (i = 0; i < priv->num_gphy_fw; i++)
2194 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2195 return err;
2196 }
2197
gswip_remove(struct platform_device * pdev)2198 static int gswip_remove(struct platform_device *pdev)
2199 {
2200 struct gswip_priv *priv = platform_get_drvdata(pdev);
2201 int i;
2202
2203 if (!priv)
2204 return 0;
2205
2206 /* disable the switch */
2207 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
2208
2209 dsa_unregister_switch(priv->ds);
2210
2211 if (priv->ds->slave_mii_bus) {
2212 mdiobus_unregister(priv->ds->slave_mii_bus);
2213 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
2214 }
2215
2216 for (i = 0; i < priv->num_gphy_fw; i++)
2217 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
2218
2219 platform_set_drvdata(pdev, NULL);
2220
2221 return 0;
2222 }
2223
gswip_shutdown(struct platform_device * pdev)2224 static void gswip_shutdown(struct platform_device *pdev)
2225 {
2226 struct gswip_priv *priv = platform_get_drvdata(pdev);
2227
2228 if (!priv)
2229 return;
2230
2231 dsa_switch_shutdown(priv->ds);
2232
2233 platform_set_drvdata(pdev, NULL);
2234 }
2235
2236 static const struct gswip_hw_info gswip_xrx200 = {
2237 .max_ports = 7,
2238 .cpu_port = 6,
2239 .ops = &gswip_xrx200_switch_ops,
2240 };
2241
2242 static const struct gswip_hw_info gswip_xrx300 = {
2243 .max_ports = 7,
2244 .cpu_port = 6,
2245 .ops = &gswip_xrx300_switch_ops,
2246 };
2247
2248 static const struct of_device_id gswip_of_match[] = {
2249 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2250 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 },
2251 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 },
2252 {},
2253 };
2254 MODULE_DEVICE_TABLE(of, gswip_of_match);
2255
2256 static struct platform_driver gswip_driver = {
2257 .probe = gswip_probe,
2258 .remove = gswip_remove,
2259 .shutdown = gswip_shutdown,
2260 .driver = {
2261 .name = "gswip",
2262 .of_match_table = gswip_of_match,
2263 },
2264 };
2265
2266 module_platform_driver(gswip_driver);
2267
2268 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
2269 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
2270 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
2271 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
2272 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
2273 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
2274 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
2275 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
2276 MODULE_LICENSE("GPL v2");
2277