1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2021 Broadcom Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/timekeeping.h>
16 #include <linux/ptp_classify.h>
17 #include "bnxt_hsi.h"
18 #include "bnxt.h"
19 #include "bnxt_hwrm.h"
20 #include "bnxt_ptp.h"
21
bnxt_ptp_parse(struct sk_buff * skb,u16 * seq_id,u16 * hdr_off)22 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
23 {
24 unsigned int ptp_class;
25 struct ptp_header *hdr;
26
27 ptp_class = ptp_classify_raw(skb);
28
29 switch (ptp_class & PTP_CLASS_VMASK) {
30 case PTP_CLASS_V1:
31 case PTP_CLASS_V2:
32 hdr = ptp_parse_header(skb, ptp_class);
33 if (!hdr)
34 return -EINVAL;
35
36 *hdr_off = (u8 *)hdr - skb->data;
37 *seq_id = ntohs(hdr->sequence_id);
38 return 0;
39 default:
40 return -ERANGE;
41 }
42 }
43
bnxt_ptp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)44 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
45 const struct timespec64 *ts)
46 {
47 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
48 ptp_info);
49 u64 ns = timespec64_to_ns(ts);
50
51 spin_lock_bh(&ptp->ptp_lock);
52 timecounter_init(&ptp->tc, &ptp->cc, ns);
53 spin_unlock_bh(&ptp->ptp_lock);
54 return 0;
55 }
56
57 /* Caller holds ptp_lock */
bnxt_refclk_read(struct bnxt * bp,struct ptp_system_timestamp * sts,u64 * ns)58 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
59 u64 *ns)
60 {
61 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
62
63 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
64 return -EIO;
65
66 ptp_read_system_prets(sts);
67 *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
68 ptp_read_system_postts(sts);
69 *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32;
70 return 0;
71 }
72
bnxt_ptp_get_current_time(struct bnxt * bp)73 static void bnxt_ptp_get_current_time(struct bnxt *bp)
74 {
75 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
76
77 if (!ptp)
78 return;
79 spin_lock_bh(&ptp->ptp_lock);
80 WRITE_ONCE(ptp->old_time, ptp->current_time);
81 bnxt_refclk_read(bp, NULL, &ptp->current_time);
82 spin_unlock_bh(&ptp->ptp_lock);
83 }
84
bnxt_hwrm_port_ts_query(struct bnxt * bp,u32 flags,u64 * ts)85 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
86 {
87 struct hwrm_port_ts_query_output *resp;
88 struct hwrm_port_ts_query_input *req;
89 int rc;
90
91 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
92 if (rc)
93 return rc;
94
95 req->flags = cpu_to_le32(flags);
96 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
97 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
98 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
99 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
100 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off);
101 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
102 }
103 resp = hwrm_req_hold(bp, req);
104
105 rc = hwrm_req_send(bp, req);
106 if (!rc)
107 *ts = le64_to_cpu(resp->ptp_msg_ts);
108 hwrm_req_drop(bp, req);
109 return rc;
110 }
111
bnxt_ptp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)112 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
113 struct timespec64 *ts,
114 struct ptp_system_timestamp *sts)
115 {
116 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
117 ptp_info);
118 u64 ns, cycles;
119 int rc;
120
121 spin_lock_bh(&ptp->ptp_lock);
122 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
123 if (rc) {
124 spin_unlock_bh(&ptp->ptp_lock);
125 return rc;
126 }
127 ns = timecounter_cyc2time(&ptp->tc, cycles);
128 spin_unlock_bh(&ptp->ptp_lock);
129 *ts = ns_to_timespec64(ns);
130
131 return 0;
132 }
133
bnxt_ptp_adjtime(struct ptp_clock_info * ptp_info,s64 delta)134 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
135 {
136 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
137 ptp_info);
138
139 spin_lock_bh(&ptp->ptp_lock);
140 timecounter_adjtime(&ptp->tc, delta);
141 spin_unlock_bh(&ptp->ptp_lock);
142 return 0;
143 }
144
bnxt_ptp_adjfreq(struct ptp_clock_info * ptp_info,s32 ppb)145 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb)
146 {
147 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
148 ptp_info);
149 struct hwrm_port_mac_cfg_input *req;
150 struct bnxt *bp = ptp->bp;
151 int rc;
152
153 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
154 if (rc)
155 return rc;
156
157 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
158 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
159 rc = hwrm_req_send(ptp->bp, req);
160 if (rc)
161 netdev_err(ptp->bp->dev,
162 "ptp adjfreq failed. rc = %d\n", rc);
163 return rc;
164 }
165
bnxt_ptp_pps_event(struct bnxt * bp,u32 data1,u32 data2)166 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
167 {
168 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
169 struct ptp_clock_event event;
170 u64 ns, pps_ts;
171
172 pps_ts = EVENT_PPS_TS(data2, data1);
173 spin_lock_bh(&ptp->ptp_lock);
174 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
175 spin_unlock_bh(&ptp->ptp_lock);
176
177 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
178 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
179 event.pps_times.ts_real = ns_to_timespec64(ns);
180 event.type = PTP_CLOCK_PPSUSR;
181 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
182 break;
183 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
184 event.timestamp = ns;
185 event.type = PTP_CLOCK_EXTTS;
186 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
187 break;
188 }
189
190 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
191 }
192
bnxt_ptp_cfg_pin(struct bnxt * bp,u8 pin,u8 usage)193 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
194 {
195 struct hwrm_func_ptp_pin_cfg_input *req;
196 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
197 u8 state = usage != BNXT_PPS_PIN_NONE;
198 u8 *pin_state, *pin_usg;
199 u32 enables;
200 int rc;
201
202 if (!TSIO_PIN_VALID(pin)) {
203 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
204 return -EOPNOTSUPP;
205 }
206
207 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
208 if (rc)
209 return rc;
210
211 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
212 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
213 req->enables = cpu_to_le32(enables);
214
215 pin_state = &req->pin0_state;
216 pin_usg = &req->pin0_usage;
217
218 *(pin_state + (pin * 2)) = state;
219 *(pin_usg + (pin * 2)) = usage;
220
221 rc = hwrm_req_send(ptp->bp, req);
222 if (rc)
223 return rc;
224
225 ptp->pps_info.pins[pin].usage = usage;
226 ptp->pps_info.pins[pin].state = state;
227
228 return 0;
229 }
230
bnxt_ptp_cfg_event(struct bnxt * bp,u8 event)231 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
232 {
233 struct hwrm_func_ptp_cfg_input *req;
234 int rc;
235
236 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
237 if (rc)
238 return rc;
239
240 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
241 req->ptp_pps_event = event;
242 return hwrm_req_send(bp, req);
243 }
244
bnxt_ptp_reapply_pps(struct bnxt * bp)245 void bnxt_ptp_reapply_pps(struct bnxt *bp)
246 {
247 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
248 struct bnxt_pps *pps;
249 u32 pin = 0;
250 int rc;
251
252 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
253 !(ptp->ptp_info.pin_config))
254 return;
255 pps = &ptp->pps_info;
256 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
257 if (pps->pins[pin].state) {
258 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
259 if (!rc && pps->pins[pin].event)
260 rc = bnxt_ptp_cfg_event(bp,
261 pps->pins[pin].event);
262 if (rc)
263 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
264 pin);
265 }
266 }
267 }
268
bnxt_get_target_cycles(struct bnxt_ptp_cfg * ptp,u64 target_ns,u64 * cycles_delta)269 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
270 u64 *cycles_delta)
271 {
272 u64 cycles_now;
273 u64 nsec_now, nsec_delta;
274 int rc;
275
276 spin_lock_bh(&ptp->ptp_lock);
277 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
278 if (rc) {
279 spin_unlock_bh(&ptp->ptp_lock);
280 return rc;
281 }
282 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
283 spin_unlock_bh(&ptp->ptp_lock);
284
285 nsec_delta = target_ns - nsec_now;
286 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
287 return 0;
288 }
289
bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg * ptp,struct ptp_clock_request * rq)290 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
291 struct ptp_clock_request *rq)
292 {
293 struct hwrm_func_ptp_cfg_input *req;
294 struct bnxt *bp = ptp->bp;
295 struct timespec64 ts;
296 u64 target_ns, delta;
297 u16 enables;
298 int rc;
299
300 ts.tv_sec = rq->perout.start.sec;
301 ts.tv_nsec = rq->perout.start.nsec;
302 target_ns = timespec64_to_ns(&ts);
303
304 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
305 if (rc)
306 return rc;
307
308 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
309 if (rc)
310 return rc;
311
312 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
313 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
314 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
315 req->enables = cpu_to_le16(enables);
316 req->ptp_pps_event = 0;
317 req->ptp_freq_adj_dll_source = 0;
318 req->ptp_freq_adj_dll_phase = 0;
319 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
320 req->ptp_freq_adj_ext_up = 0;
321 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
322
323 return hwrm_req_send(bp, req);
324 }
325
bnxt_ptp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)326 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
327 struct ptp_clock_request *rq, int on)
328 {
329 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
330 ptp_info);
331 struct bnxt *bp = ptp->bp;
332 u8 pin_id;
333 int rc;
334
335 switch (rq->type) {
336 case PTP_CLK_REQ_EXTTS:
337 /* Configure an External PPS IN */
338 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
339 rq->extts.index);
340 if (!on)
341 break;
342 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
343 if (rc)
344 return rc;
345 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
346 if (!rc)
347 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
348 return rc;
349 case PTP_CLK_REQ_PEROUT:
350 /* Configure a Periodic PPS OUT */
351 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
352 rq->perout.index);
353 if (!on)
354 break;
355
356 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
357 if (!rc)
358 rc = bnxt_ptp_perout_cfg(ptp, rq);
359
360 return rc;
361 case PTP_CLK_REQ_PPS:
362 /* Configure PHC PPS IN */
363 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
364 if (rc)
365 return rc;
366 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
367 if (!rc)
368 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
369 return rc;
370 default:
371 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
372 return -EOPNOTSUPP;
373 }
374
375 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
376 }
377
bnxt_hwrm_ptp_cfg(struct bnxt * bp)378 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
379 {
380 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
381 struct hwrm_port_mac_cfg_input *req;
382 u32 flags = 0;
383 int rc;
384
385 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
386 if (rc)
387 return rc;
388
389 if (ptp->rx_filter)
390 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
391 else
392 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
393 if (ptp->tx_tstamp_en)
394 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
395 else
396 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
397 req->flags = cpu_to_le32(flags);
398 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
399 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
400
401 return hwrm_req_send(bp, req);
402 }
403
bnxt_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)404 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
405 {
406 struct bnxt *bp = netdev_priv(dev);
407 struct hwtstamp_config stmpconf;
408 struct bnxt_ptp_cfg *ptp;
409 u16 old_rxctl;
410 int old_rx_filter, rc;
411 u8 old_tx_tstamp_en;
412
413 ptp = bp->ptp_cfg;
414 if (!ptp)
415 return -EOPNOTSUPP;
416
417 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
418 return -EFAULT;
419
420 if (stmpconf.flags)
421 return -EINVAL;
422
423 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
424 stmpconf.tx_type != HWTSTAMP_TX_OFF)
425 return -ERANGE;
426
427 old_rx_filter = ptp->rx_filter;
428 old_rxctl = ptp->rxctl;
429 old_tx_tstamp_en = ptp->tx_tstamp_en;
430 switch (stmpconf.rx_filter) {
431 case HWTSTAMP_FILTER_NONE:
432 ptp->rxctl = 0;
433 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
434 break;
435 case HWTSTAMP_FILTER_PTP_V2_EVENT:
436 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
437 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
438 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
439 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
440 break;
441 case HWTSTAMP_FILTER_PTP_V2_SYNC:
442 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
443 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
444 ptp->rxctl = BNXT_PTP_MSG_SYNC;
445 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
446 break;
447 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
448 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
449 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
450 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
451 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
452 break;
453 default:
454 return -ERANGE;
455 }
456
457 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
458 ptp->tx_tstamp_en = 1;
459 else
460 ptp->tx_tstamp_en = 0;
461
462 rc = bnxt_hwrm_ptp_cfg(bp);
463 if (rc)
464 goto ts_set_err;
465
466 stmpconf.rx_filter = ptp->rx_filter;
467 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
468 -EFAULT : 0;
469
470 ts_set_err:
471 ptp->rx_filter = old_rx_filter;
472 ptp->rxctl = old_rxctl;
473 ptp->tx_tstamp_en = old_tx_tstamp_en;
474 return rc;
475 }
476
bnxt_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)477 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
478 {
479 struct bnxt *bp = netdev_priv(dev);
480 struct hwtstamp_config stmpconf;
481 struct bnxt_ptp_cfg *ptp;
482
483 ptp = bp->ptp_cfg;
484 if (!ptp)
485 return -EOPNOTSUPP;
486
487 stmpconf.flags = 0;
488 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
489
490 stmpconf.rx_filter = ptp->rx_filter;
491 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
492 -EFAULT : 0;
493 }
494
bnxt_map_regs(struct bnxt * bp,u32 * reg_arr,int count,int reg_win)495 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
496 {
497 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
498 u32 win_off;
499 int i;
500
501 for (i = 0; i < count; i++) {
502 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
503 return -ERANGE;
504 }
505 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
506 writel(reg_base, bp->bar0 + win_off);
507 return 0;
508 }
509
bnxt_map_ptp_regs(struct bnxt * bp)510 static int bnxt_map_ptp_regs(struct bnxt *bp)
511 {
512 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
513 u32 *reg_arr;
514 int rc, i;
515
516 reg_arr = ptp->refclk_regs;
517 if (bp->flags & BNXT_FLAG_CHIP_P5) {
518 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
519 if (rc)
520 return rc;
521 for (i = 0; i < 2; i++)
522 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
523 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
524 return 0;
525 }
526 return -ENODEV;
527 }
528
bnxt_unmap_ptp_regs(struct bnxt * bp)529 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
530 {
531 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
532 (BNXT_PTP_GRC_WIN - 1) * 4);
533 }
534
bnxt_cc_read(const struct cyclecounter * cc)535 static u64 bnxt_cc_read(const struct cyclecounter *cc)
536 {
537 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
538 u64 ns = 0;
539
540 bnxt_refclk_read(ptp->bp, NULL, &ns);
541 return ns;
542 }
543
bnxt_stamp_tx_skb(struct bnxt * bp,struct sk_buff * skb)544 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
545 {
546 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
547 struct skb_shared_hwtstamps timestamp;
548 u64 ts = 0, ns = 0;
549 int rc;
550
551 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
552 if (!rc) {
553 memset(×tamp, 0, sizeof(timestamp));
554 spin_lock_bh(&ptp->ptp_lock);
555 ns = timecounter_cyc2time(&ptp->tc, ts);
556 spin_unlock_bh(&ptp->ptp_lock);
557 timestamp.hwtstamp = ns_to_ktime(ns);
558 skb_tstamp_tx(ptp->tx_skb, ×tamp);
559 } else {
560 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
561 rc);
562 }
563
564 dev_kfree_skb_any(ptp->tx_skb);
565 ptp->tx_skb = NULL;
566 atomic_inc(&ptp->tx_avail);
567 }
568
bnxt_ptp_ts_aux_work(struct ptp_clock_info * ptp_info)569 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
570 {
571 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
572 ptp_info);
573 unsigned long now = jiffies;
574 struct bnxt *bp = ptp->bp;
575
576 if (ptp->tx_skb)
577 bnxt_stamp_tx_skb(bp, ptp->tx_skb);
578
579 if (!time_after_eq(now, ptp->next_period))
580 return ptp->next_period - now;
581
582 bnxt_ptp_get_current_time(bp);
583 ptp->next_period = now + HZ;
584 if (time_after_eq(now, ptp->next_overflow_check)) {
585 spin_lock_bh(&ptp->ptp_lock);
586 timecounter_read(&ptp->tc);
587 spin_unlock_bh(&ptp->ptp_lock);
588 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
589 }
590 return HZ;
591 }
592
bnxt_get_tx_ts_p5(struct bnxt * bp,struct sk_buff * skb)593 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
594 {
595 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
596
597 if (ptp->tx_skb) {
598 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
599 return -EBUSY;
600 }
601 ptp->tx_skb = skb;
602 ptp_schedule_worker(ptp->ptp_clock, 0);
603 return 0;
604 }
605
bnxt_get_rx_ts_p5(struct bnxt * bp,u64 * ts,u32 pkt_ts)606 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
607 {
608 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
609 u64 time;
610
611 if (!ptp)
612 return -ENODEV;
613
614 BNXT_READ_TIME64(ptp, time, ptp->old_time);
615 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
616 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
617 *ts += BNXT_LO_TIMER_MASK + 1;
618
619 return 0;
620 }
621
622 static const struct ptp_clock_info bnxt_ptp_caps = {
623 .owner = THIS_MODULE,
624 .name = "bnxt clock",
625 .max_adj = BNXT_MAX_PHC_DRIFT,
626 .n_alarm = 0,
627 .n_ext_ts = 0,
628 .n_per_out = 0,
629 .n_pins = 0,
630 .pps = 0,
631 .adjfreq = bnxt_ptp_adjfreq,
632 .adjtime = bnxt_ptp_adjtime,
633 .do_aux_work = bnxt_ptp_ts_aux_work,
634 .gettimex64 = bnxt_ptp_gettimex,
635 .settime64 = bnxt_ptp_settime,
636 .enable = bnxt_ptp_enable,
637 };
638
bnxt_ptp_verify(struct ptp_clock_info * ptp_info,unsigned int pin,enum ptp_pin_function func,unsigned int chan)639 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
640 enum ptp_pin_function func, unsigned int chan)
641 {
642 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
643 ptp_info);
644 /* Allow only PPS pin function configuration */
645 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
646 func != PTP_PF_PHYSYNC)
647 return 0;
648 else
649 return -EOPNOTSUPP;
650 }
651
bnxt_ptp_pps_init(struct bnxt * bp)652 static int bnxt_ptp_pps_init(struct bnxt *bp)
653 {
654 struct hwrm_func_ptp_pin_qcfg_output *resp;
655 struct hwrm_func_ptp_pin_qcfg_input *req;
656 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
657 struct ptp_clock_info *ptp_info;
658 struct bnxt_pps *pps_info;
659 u8 *pin_usg;
660 u32 i, rc;
661
662 /* Query current/default PIN CFG */
663 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
664 if (rc)
665 return rc;
666
667 resp = hwrm_req_hold(bp, req);
668 rc = hwrm_req_send(bp, req);
669 if (rc || !resp->num_pins) {
670 hwrm_req_drop(bp, req);
671 return -EOPNOTSUPP;
672 }
673
674 ptp_info = &ptp->ptp_info;
675 pps_info = &ptp->pps_info;
676 pps_info->num_pins = resp->num_pins;
677 ptp_info->n_pins = pps_info->num_pins;
678 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
679 sizeof(*ptp_info->pin_config),
680 GFP_KERNEL);
681 if (!ptp_info->pin_config) {
682 hwrm_req_drop(bp, req);
683 return -ENOMEM;
684 }
685
686 /* Report the TSIO capability to kernel */
687 pin_usg = &resp->pin0_usage;
688 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
689 snprintf(ptp_info->pin_config[i].name,
690 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
691 ptp_info->pin_config[i].index = i;
692 ptp_info->pin_config[i].chan = i;
693 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
694 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
695 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
696 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
697 else
698 ptp_info->pin_config[i].func = PTP_PF_NONE;
699
700 pps_info->pins[i].usage = *pin_usg;
701 }
702 hwrm_req_drop(bp, req);
703
704 /* Only 1 each of ext_ts and per_out pins is available in HW */
705 ptp_info->n_ext_ts = 1;
706 ptp_info->n_per_out = 1;
707 ptp_info->pps = 1;
708 ptp_info->verify = bnxt_ptp_verify;
709
710 return 0;
711 }
712
bnxt_pps_config_ok(struct bnxt * bp)713 static bool bnxt_pps_config_ok(struct bnxt *bp)
714 {
715 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
716
717 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
718 }
719
bnxt_ptp_init(struct bnxt * bp)720 int bnxt_ptp_init(struct bnxt *bp)
721 {
722 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
723 int rc;
724
725 if (!ptp)
726 return 0;
727
728 rc = bnxt_map_ptp_regs(bp);
729 if (rc)
730 return rc;
731
732 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
733 return 0;
734
735 if (ptp->ptp_clock) {
736 ptp_clock_unregister(ptp->ptp_clock);
737 ptp->ptp_clock = NULL;
738 kfree(ptp->ptp_info.pin_config);
739 ptp->ptp_info.pin_config = NULL;
740 }
741 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
742 spin_lock_init(&ptp->ptp_lock);
743
744 memset(&ptp->cc, 0, sizeof(ptp->cc));
745 ptp->cc.read = bnxt_cc_read;
746 ptp->cc.mask = CYCLECOUNTER_MASK(48);
747 ptp->cc.shift = 0;
748 ptp->cc.mult = 1;
749
750 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
751 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
752
753 ptp->ptp_info = bnxt_ptp_caps;
754 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
755 if (bnxt_ptp_pps_init(bp))
756 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
757 }
758 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
759 if (IS_ERR(ptp->ptp_clock)) {
760 int err = PTR_ERR(ptp->ptp_clock);
761
762 ptp->ptp_clock = NULL;
763 bnxt_unmap_ptp_regs(bp);
764 return err;
765 }
766 if (bp->flags & BNXT_FLAG_CHIP_P5) {
767 spin_lock_bh(&ptp->ptp_lock);
768 bnxt_refclk_read(bp, NULL, &ptp->current_time);
769 WRITE_ONCE(ptp->old_time, ptp->current_time);
770 spin_unlock_bh(&ptp->ptp_lock);
771 ptp_schedule_worker(ptp->ptp_clock, 0);
772 }
773 return 0;
774 }
775
bnxt_ptp_clear(struct bnxt * bp)776 void bnxt_ptp_clear(struct bnxt *bp)
777 {
778 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
779
780 if (!ptp)
781 return;
782
783 if (ptp->ptp_clock)
784 ptp_clock_unregister(ptp->ptp_clock);
785
786 ptp->ptp_clock = NULL;
787 kfree(ptp->ptp_info.pin_config);
788 ptp->ptp_info.pin_config = NULL;
789
790 if (ptp->tx_skb) {
791 dev_kfree_skb_any(ptp->tx_skb);
792 ptp->tx_skb = NULL;
793 }
794 bnxt_unmap_ptp_regs(bp);
795 }
796