1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/acpi.h>
14 #include <linux/bitfield.h>
15 #include <linux/bits.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/limits.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/rtc.h>
25 #include <linux/suspend.h>
26 #include <linux/seq_file.h>
27 #include <linux/uaccess.h>
28
29 /* SMU communication registers */
30 #define AMD_PMC_REGISTER_MESSAGE 0x538
31 #define AMD_PMC_REGISTER_RESPONSE 0x980
32 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
33
34 /* PMC Scratch Registers */
35 #define AMD_PMC_SCRATCH_REG_CZN 0x94
36 #define AMD_PMC_SCRATCH_REG_YC 0xD14
37
38 /* Base address of SMU for mapping physical address to virtual address */
39 #define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
40 #define AMD_PMC_SMU_INDEX_DATA 0xBC
41 #define AMD_PMC_MAPPING_SIZE 0x01000
42 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
43 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
44 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
45 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
46 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
47
48 /* SMU Response Codes */
49 #define AMD_PMC_RESULT_OK 0x01
50 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
51 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
52 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
53 #define AMD_PMC_RESULT_FAILED 0xFF
54
55 /* FCH SSC Registers */
56 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
57 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
58 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
59 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
60 #define FCH_SSC_MAPPING_SIZE 0x800
61 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
62 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
63
64 /* SMU Message Definations */
65 #define SMU_MSG_GETSMUVERSION 0x02
66 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
67 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
68 #define SMU_MSG_LOG_START 0x06
69 #define SMU_MSG_LOG_RESET 0x07
70 #define SMU_MSG_LOG_DUMP_DATA 0x08
71 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
72 /* List of supported CPU ids */
73 #define AMD_CPU_ID_RV 0x15D0
74 #define AMD_CPU_ID_RN 0x1630
75 #define AMD_CPU_ID_PCO AMD_CPU_ID_RV
76 #define AMD_CPU_ID_CZN AMD_CPU_ID_RN
77 #define AMD_CPU_ID_YC 0x14B5
78
79 #define PMC_MSG_DELAY_MIN_US 50
80 #define RESPONSE_REGISTER_LOOP_MAX 20000
81
82 #define SOC_SUBSYSTEM_IP_MAX 12
83 #define DELAY_MIN_US 2000
84 #define DELAY_MAX_US 3000
85 enum amd_pmc_def {
86 MSG_TEST = 0x01,
87 MSG_OS_HINT_PCO,
88 MSG_OS_HINT_RN,
89 };
90
91 struct amd_pmc_bit_map {
92 const char *name;
93 u32 bit_mask;
94 };
95
96 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
97 {"DISPLAY", BIT(0)},
98 {"CPU", BIT(1)},
99 {"GFX", BIT(2)},
100 {"VDD", BIT(3)},
101 {"ACP", BIT(4)},
102 {"VCN", BIT(5)},
103 {"ISP", BIT(6)},
104 {"NBIO", BIT(7)},
105 {"DF", BIT(8)},
106 {"USB0", BIT(9)},
107 {"USB1", BIT(10)},
108 {"LAPIC", BIT(11)},
109 {}
110 };
111
112 struct amd_pmc_dev {
113 void __iomem *regbase;
114 void __iomem *smu_virt_addr;
115 void __iomem *fch_virt_addr;
116 u32 base_addr;
117 u32 cpu_id;
118 u32 active_ips;
119 /* SMU version information */
120 u16 major;
121 u16 minor;
122 u16 rev;
123 struct device *dev;
124 struct mutex lock; /* generic mutex lock */
125 #if IS_ENABLED(CONFIG_DEBUG_FS)
126 struct dentry *dbgfs_dir;
127 #endif /* CONFIG_DEBUG_FS */
128 };
129
130 static struct amd_pmc_dev pmc;
131 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
132
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)133 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
134 {
135 return ioread32(dev->regbase + reg_offset);
136 }
137
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)138 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
139 {
140 iowrite32(val, dev->regbase + reg_offset);
141 }
142
143 struct smu_metrics {
144 u32 table_version;
145 u32 hint_count;
146 u32 s0i3_last_entry_status;
147 u32 timein_s0i2;
148 u64 timeentering_s0i3_lastcapture;
149 u64 timeentering_s0i3_totaltime;
150 u64 timeto_resume_to_os_lastcapture;
151 u64 timeto_resume_to_os_totaltime;
152 u64 timein_s0i3_lastcapture;
153 u64 timein_s0i3_totaltime;
154 u64 timein_swdrips_lastcapture;
155 u64 timein_swdrips_totaltime;
156 u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
157 u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
158 } __packed;
159
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)160 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
161 {
162 int rc;
163 u32 val;
164
165 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
166 if (rc)
167 return rc;
168
169 dev->major = (val >> 16) & GENMASK(15, 0);
170 dev->minor = (val >> 8) & GENMASK(7, 0);
171 dev->rev = (val >> 0) & GENMASK(7, 0);
172
173 dev_dbg(dev->dev, "SMU version is %u.%u.%u\n", dev->major, dev->minor, dev->rev);
174
175 return 0;
176 }
177
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)178 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
179 struct seq_file *s)
180 {
181 u32 val;
182
183 switch (pdev->cpu_id) {
184 case AMD_CPU_ID_CZN:
185 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
186 break;
187 case AMD_CPU_ID_YC:
188 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
189 break;
190 default:
191 return -EINVAL;
192 }
193
194 if (dev)
195 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
196
197 if (s)
198 seq_printf(s, "SMU idlemask : 0x%x\n", val);
199
200 return 0;
201 }
202
203 #ifdef CONFIG_DEBUG_FS
smu_fw_info_show(struct seq_file * s,void * unused)204 static int smu_fw_info_show(struct seq_file *s, void *unused)
205 {
206 struct amd_pmc_dev *dev = s->private;
207 struct smu_metrics table;
208 int idx;
209
210 if (dev->cpu_id == AMD_CPU_ID_PCO)
211 return -EINVAL;
212
213 memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
214
215 seq_puts(s, "\n=== SMU Statistics ===\n");
216 seq_printf(s, "Table Version: %d\n", table.table_version);
217 seq_printf(s, "Hint Count: %d\n", table.hint_count);
218 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
219 "Unknown/Fail");
220 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
221 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
222 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
223 table.timeto_resume_to_os_lastcapture);
224
225 seq_puts(s, "\n=== Active time (in us) ===\n");
226 for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
227 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
228 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
229 table.timecondition_notmet_lastcapture[idx]);
230 }
231
232 return 0;
233 }
234 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
235
s0ix_stats_show(struct seq_file * s,void * unused)236 static int s0ix_stats_show(struct seq_file *s, void *unused)
237 {
238 struct amd_pmc_dev *dev = s->private;
239 u64 entry_time, exit_time, residency;
240
241 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
242 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
243
244 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
245 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
246
247 /* It's in 48MHz. We need to convert it */
248 residency = exit_time - entry_time;
249 do_div(residency, 48);
250
251 seq_puts(s, "=== S0ix statistics ===\n");
252 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
253 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
254 seq_printf(s, "Residency Time: %lld\n", residency);
255
256 return 0;
257 }
258 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
259
amd_pmc_idlemask_show(struct seq_file * s,void * unused)260 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
261 {
262 struct amd_pmc_dev *dev = s->private;
263 int rc;
264
265 if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
266 rc = amd_pmc_idlemask_read(dev, NULL, s);
267 if (rc)
268 return rc;
269 } else {
270 seq_puts(s, "Unsupported SMU version for Idlemask\n");
271 }
272
273 return 0;
274 }
275 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
276
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)277 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
278 {
279 debugfs_remove_recursive(dev->dbgfs_dir);
280 }
281
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)282 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
283 {
284 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
285 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
286 &smu_fw_info_fops);
287 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
288 &s0ix_stats_fops);
289 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
290 &amd_pmc_idlemask_fops);
291 }
292 #else
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)293 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
294 {
295 }
296
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)297 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
298 {
299 }
300 #endif /* CONFIG_DEBUG_FS */
301
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)302 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
303 {
304 u32 phys_addr_low, phys_addr_hi;
305 u64 smu_phys_addr;
306
307 if (dev->cpu_id == AMD_CPU_ID_PCO)
308 return -EINVAL;
309
310 /* Get Active devices list from SMU */
311 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
312
313 /* Get dram address */
314 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
315 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
316 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
317
318 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
319 if (!dev->smu_virt_addr)
320 return -ENOMEM;
321
322 /* Start the logging */
323 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
324
325 return 0;
326 }
327
amd_pmc_dump_registers(struct amd_pmc_dev * dev)328 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
329 {
330 u32 value;
331
332 value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
333 dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
334
335 value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
336 dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
337
338 value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
339 dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
340 }
341
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)342 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
343 {
344 int rc;
345 u32 val;
346
347 mutex_lock(&dev->lock);
348 /* Wait until we get a valid response */
349 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
350 val, val != 0, PMC_MSG_DELAY_MIN_US,
351 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
352 if (rc) {
353 dev_err(dev->dev, "failed to talk to SMU\n");
354 goto out_unlock;
355 }
356
357 /* Write zero to response register */
358 amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
359
360 /* Write argument into response register */
361 amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, arg);
362
363 /* Write message ID to message ID register */
364 amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
365
366 /* Wait until we get a valid response */
367 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
368 val, val != 0, PMC_MSG_DELAY_MIN_US,
369 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
370 if (rc) {
371 dev_err(dev->dev, "SMU response timed out\n");
372 goto out_unlock;
373 }
374
375 switch (val) {
376 case AMD_PMC_RESULT_OK:
377 if (ret) {
378 /* PMFW may take longer time to return back the data */
379 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
380 *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
381 }
382 break;
383 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
384 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
385 rc = -EBUSY;
386 goto out_unlock;
387 case AMD_PMC_RESULT_CMD_UNKNOWN:
388 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
389 rc = -EINVAL;
390 goto out_unlock;
391 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
392 case AMD_PMC_RESULT_FAILED:
393 default:
394 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
395 rc = -EIO;
396 goto out_unlock;
397 }
398
399 out_unlock:
400 mutex_unlock(&dev->lock);
401 amd_pmc_dump_registers(dev);
402 return rc;
403 }
404
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)405 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
406 {
407 switch (dev->cpu_id) {
408 case AMD_CPU_ID_PCO:
409 return MSG_OS_HINT_PCO;
410 case AMD_CPU_ID_RN:
411 case AMD_CPU_ID_YC:
412 return MSG_OS_HINT_RN;
413 }
414 return -EINVAL;
415 }
416
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)417 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
418 {
419 struct rtc_device *rtc_device;
420 time64_t then, now, duration;
421 struct rtc_wkalrm alarm;
422 struct rtc_time tm;
423 int rc;
424
425 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
426 return 0;
427
428 rtc_device = rtc_class_open("rtc0");
429 if (!rtc_device)
430 return 0;
431 rc = rtc_read_alarm(rtc_device, &alarm);
432 if (rc)
433 return rc;
434 if (!alarm.enabled) {
435 dev_dbg(pdev->dev, "alarm not enabled\n");
436 return 0;
437 }
438 rc = rtc_read_time(rtc_device, &tm);
439 if (rc)
440 return rc;
441 then = rtc_tm_to_time64(&alarm.time);
442 now = rtc_tm_to_time64(&tm);
443 duration = then-now;
444
445 /* in the past */
446 if (then < now)
447 return 0;
448
449 /* will be stored in upper 16 bits of s0i3 hint argument,
450 * so timer wakeup from s0i3 is limited to ~18 hours or less
451 */
452 if (duration <= 4 || duration > U16_MAX)
453 return -EINVAL;
454
455 *arg |= (duration << 16);
456 rc = rtc_alarm_irq_enable(rtc_device, 0);
457 dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
458
459 return rc;
460 }
461
amd_pmc_suspend(struct device * dev)462 static int __maybe_unused amd_pmc_suspend(struct device *dev)
463 {
464 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
465 int rc;
466 u8 msg;
467 u32 arg = 1;
468
469 /* Reset and Start SMU logging - to monitor the s0i3 stats */
470 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
471 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
472
473 /* Activate CZN specific RTC functionality */
474 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
475 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
476 if (rc < 0)
477 return rc;
478 }
479
480 /* Dump the IdleMask before we send hint to SMU */
481 amd_pmc_idlemask_read(pdev, dev, NULL);
482 msg = amd_pmc_get_os_hint(pdev);
483 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
484 if (rc)
485 dev_err(pdev->dev, "suspend failed\n");
486
487 return rc;
488 }
489
amd_pmc_resume(struct device * dev)490 static int __maybe_unused amd_pmc_resume(struct device *dev)
491 {
492 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
493 int rc;
494 u8 msg;
495
496 msg = amd_pmc_get_os_hint(pdev);
497 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
498 if (rc)
499 dev_err(pdev->dev, "resume failed\n");
500
501 /* Let SMU know that we are looking for stats */
502 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
503
504 /* Dump the IdleMask to see the blockers */
505 amd_pmc_idlemask_read(pdev, dev, NULL);
506
507 return 0;
508 }
509
510 static const struct dev_pm_ops amd_pmc_pm_ops = {
511 .suspend_noirq = amd_pmc_suspend,
512 .resume_noirq = amd_pmc_resume,
513 };
514
515 static const struct pci_device_id pmc_pci_ids[] = {
516 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
517 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
518 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
519 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
520 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
521 { }
522 };
523
amd_pmc_probe(struct platform_device * pdev)524 static int amd_pmc_probe(struct platform_device *pdev)
525 {
526 struct amd_pmc_dev *dev = &pmc;
527 struct pci_dev *rdev;
528 u32 base_addr_lo, base_addr_hi;
529 u64 base_addr, fch_phys_addr;
530 int err;
531 u32 val;
532
533 dev->dev = &pdev->dev;
534
535 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
536 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
537 pci_dev_put(rdev);
538 return -ENODEV;
539 }
540
541 dev->cpu_id = rdev->device;
542 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
543 if (err) {
544 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
545 pci_dev_put(rdev);
546 return pcibios_err_to_errno(err);
547 }
548
549 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
550 if (err) {
551 pci_dev_put(rdev);
552 return pcibios_err_to_errno(err);
553 }
554
555 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
556
557 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
558 if (err) {
559 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
560 pci_dev_put(rdev);
561 return pcibios_err_to_errno(err);
562 }
563
564 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
565 if (err) {
566 pci_dev_put(rdev);
567 return pcibios_err_to_errno(err);
568 }
569
570 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
571 pci_dev_put(rdev);
572 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
573
574 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
575 AMD_PMC_MAPPING_SIZE);
576 if (!dev->regbase)
577 return -ENOMEM;
578
579 mutex_init(&dev->lock);
580
581 /* Use FCH registers to get the S0ix stats */
582 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
583 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
584 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
585 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
586 if (!dev->fch_virt_addr)
587 return -ENOMEM;
588
589 /* Use SMU to get the s0i3 debug stats */
590 err = amd_pmc_setup_smu_logging(dev);
591 if (err)
592 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
593
594 amd_pmc_get_smu_version(dev);
595 platform_set_drvdata(pdev, dev);
596 amd_pmc_dbgfs_register(dev);
597 return 0;
598 }
599
amd_pmc_remove(struct platform_device * pdev)600 static int amd_pmc_remove(struct platform_device *pdev)
601 {
602 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
603
604 amd_pmc_dbgfs_unregister(dev);
605 mutex_destroy(&dev->lock);
606 return 0;
607 }
608
609 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
610 {"AMDI0005", 0},
611 {"AMDI0006", 0},
612 {"AMDI0007", 0},
613 {"AMD0004", 0},
614 {"AMD0005", 0},
615 { }
616 };
617 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
618
619 static struct platform_driver amd_pmc_driver = {
620 .driver = {
621 .name = "amd_pmc",
622 .acpi_match_table = amd_pmc_acpi_ids,
623 .pm = &amd_pmc_pm_ops,
624 },
625 .probe = amd_pmc_probe,
626 .remove = amd_pmc_remove,
627 };
628 module_platform_driver(amd_pmc_driver);
629
630 MODULE_LICENSE("GPL v2");
631 MODULE_DESCRIPTION("AMD PMC Driver");
632