1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2017-2019, Linaro Ltd.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/err.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/random.h>
12 #include <linux/slab.h>
13 #include <linux/soc/qcom/smem.h>
14 #include <linux/string.h>
15 #include <linux/sys_soc.h>
16 #include <linux/types.h>
17
18 #include <asm/unaligned.h>
19
20 /*
21 * SoC version type with major number in the upper 16 bits and minor
22 * number in the lower 16 bits.
23 */
24 #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
25 #define SOCINFO_MINOR(ver) ((ver) & 0xffff)
26 #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
27
28 #define SMEM_SOCINFO_BUILD_ID_LENGTH 32
29 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32
30
31 /*
32 * SMEM item id, used to acquire handles to respective
33 * SMEM region.
34 */
35 #define SMEM_HW_SW_BUILD_ID 137
36
37 #ifdef CONFIG_DEBUG_FS
38 #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
39 #define SMEM_IMAGE_VERSION_SIZE 4096
40 #define SMEM_IMAGE_VERSION_NAME_SIZE 75
41 #define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
42 #define SMEM_IMAGE_VERSION_OEM_SIZE 32
43
44 /*
45 * SMEM Image table indices
46 */
47 #define SMEM_IMAGE_TABLE_BOOT_INDEX 0
48 #define SMEM_IMAGE_TABLE_TZ_INDEX 1
49 #define SMEM_IMAGE_TABLE_RPM_INDEX 3
50 #define SMEM_IMAGE_TABLE_APPS_INDEX 10
51 #define SMEM_IMAGE_TABLE_MPSS_INDEX 11
52 #define SMEM_IMAGE_TABLE_ADSP_INDEX 12
53 #define SMEM_IMAGE_TABLE_CNSS_INDEX 13
54 #define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
55 #define SMEM_IMAGE_VERSION_TABLE 469
56
57 /*
58 * SMEM Image table names
59 */
60 static const char *const socinfo_image_names[] = {
61 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
62 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
63 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
64 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
65 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
66 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
67 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
68 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
69 };
70
71 static const char *const pmic_models[] = {
72 [0] = "Unknown PMIC model",
73 [1] = "PM8941",
74 [2] = "PM8841",
75 [3] = "PM8019",
76 [4] = "PM8226",
77 [5] = "PM8110",
78 [6] = "PMA8084",
79 [7] = "PMI8962",
80 [8] = "PMD9635",
81 [9] = "PM8994",
82 [10] = "PMI8994",
83 [11] = "PM8916",
84 [12] = "PM8004",
85 [13] = "PM8909/PM8058",
86 [14] = "PM8028",
87 [15] = "PM8901",
88 [16] = "PM8950/PM8027",
89 [17] = "PMI8950/ISL9519",
90 [18] = "PMK8001/PM8921",
91 [19] = "PMI8996/PM8018",
92 [20] = "PM8998/PM8015",
93 [21] = "PMI8998/PM8014",
94 [22] = "PM8821",
95 [23] = "PM8038",
96 [24] = "PM8005/PM8922",
97 [25] = "PM8917",
98 [26] = "PM660L",
99 [27] = "PM660",
100 [30] = "PM8150",
101 [31] = "PM8150L",
102 [32] = "PM8150B",
103 [33] = "PMK8002",
104 [36] = "PM8009",
105 [38] = "PM8150C",
106 [41] = "SMB2351",
107 };
108 #endif /* CONFIG_DEBUG_FS */
109
110 /* Socinfo SMEM item structure */
111 struct socinfo {
112 __le32 fmt;
113 __le32 id;
114 __le32 ver;
115 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
116 /* Version 2 */
117 __le32 raw_id;
118 __le32 raw_ver;
119 /* Version 3 */
120 __le32 hw_plat;
121 /* Version 4 */
122 __le32 plat_ver;
123 /* Version 5 */
124 __le32 accessory_chip;
125 /* Version 6 */
126 __le32 hw_plat_subtype;
127 /* Version 7 */
128 __le32 pmic_model;
129 __le32 pmic_die_rev;
130 /* Version 8 */
131 __le32 pmic_model_1;
132 __le32 pmic_die_rev_1;
133 __le32 pmic_model_2;
134 __le32 pmic_die_rev_2;
135 /* Version 9 */
136 __le32 foundry_id;
137 /* Version 10 */
138 __le32 serial_num;
139 /* Version 11 */
140 __le32 num_pmics;
141 __le32 pmic_array_offset;
142 /* Version 12 */
143 __le32 chip_family;
144 __le32 raw_device_family;
145 __le32 raw_device_num;
146 /* Version 13 */
147 __le32 nproduct_id;
148 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
149 /* Version 14 */
150 __le32 num_clusters;
151 __le32 ncluster_array_offset;
152 __le32 num_defective_parts;
153 __le32 ndefective_parts_array_offset;
154 /* Version 15 */
155 __le32 nmodem_supported;
156 };
157
158 #ifdef CONFIG_DEBUG_FS
159 struct socinfo_params {
160 u32 raw_device_family;
161 u32 hw_plat_subtype;
162 u32 accessory_chip;
163 u32 raw_device_num;
164 u32 chip_family;
165 u32 foundry_id;
166 u32 plat_ver;
167 u32 raw_ver;
168 u32 hw_plat;
169 u32 fmt;
170 u32 nproduct_id;
171 u32 num_clusters;
172 u32 ncluster_array_offset;
173 u32 num_defective_parts;
174 u32 ndefective_parts_array_offset;
175 u32 nmodem_supported;
176 };
177
178 struct smem_image_version {
179 char name[SMEM_IMAGE_VERSION_NAME_SIZE];
180 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE];
181 char pad;
182 char oem[SMEM_IMAGE_VERSION_OEM_SIZE];
183 };
184 #endif /* CONFIG_DEBUG_FS */
185
186 struct qcom_socinfo {
187 struct soc_device *soc_dev;
188 struct soc_device_attribute attr;
189 #ifdef CONFIG_DEBUG_FS
190 struct dentry *dbg_root;
191 struct socinfo_params info;
192 #endif /* CONFIG_DEBUG_FS */
193 };
194
195 struct soc_id {
196 unsigned int id;
197 const char *name;
198 };
199
200 static const struct soc_id soc_id[] = {
201 { 87, "MSM8960" },
202 { 109, "APQ8064" },
203 { 122, "MSM8660A" },
204 { 123, "MSM8260A" },
205 { 124, "APQ8060A" },
206 { 126, "MSM8974" },
207 { 130, "MPQ8064" },
208 { 138, "MSM8960AB" },
209 { 139, "APQ8060AB" },
210 { 140, "MSM8260AB" },
211 { 141, "MSM8660AB" },
212 { 145, "MSM8626" },
213 { 147, "MSM8610" },
214 { 153, "APQ8064AB" },
215 { 158, "MSM8226" },
216 { 159, "MSM8526" },
217 { 161, "MSM8110" },
218 { 162, "MSM8210" },
219 { 163, "MSM8810" },
220 { 164, "MSM8212" },
221 { 165, "MSM8612" },
222 { 166, "MSM8112" },
223 { 168, "MSM8225Q" },
224 { 169, "MSM8625Q" },
225 { 170, "MSM8125Q" },
226 { 172, "APQ8064AA" },
227 { 178, "APQ8084" },
228 { 184, "APQ8074" },
229 { 185, "MSM8274" },
230 { 186, "MSM8674" },
231 { 194, "MSM8974PRO" },
232 { 198, "MSM8126" },
233 { 199, "APQ8026" },
234 { 200, "MSM8926" },
235 { 205, "MSM8326" },
236 { 206, "MSM8916" },
237 { 207, "MSM8994" },
238 { 208, "APQ8074-AA" },
239 { 209, "APQ8074-AB" },
240 { 210, "APQ8074PRO" },
241 { 211, "MSM8274-AA" },
242 { 212, "MSM8274-AB" },
243 { 213, "MSM8274PRO" },
244 { 214, "MSM8674-AA" },
245 { 215, "MSM8674-AB" },
246 { 216, "MSM8674PRO" },
247 { 217, "MSM8974-AA" },
248 { 218, "MSM8974-AB" },
249 { 219, "APQ8028" },
250 { 220, "MSM8128" },
251 { 221, "MSM8228" },
252 { 222, "MSM8528" },
253 { 223, "MSM8628" },
254 { 224, "MSM8928" },
255 { 225, "MSM8510" },
256 { 226, "MSM8512" },
257 { 233, "MSM8936" },
258 { 239, "MSM8939" },
259 { 240, "APQ8036" },
260 { 241, "APQ8039" },
261 { 246, "MSM8996" },
262 { 247, "APQ8016" },
263 { 248, "MSM8216" },
264 { 249, "MSM8116" },
265 { 250, "MSM8616" },
266 { 251, "MSM8992" },
267 { 253, "APQ8094" },
268 { 290, "MDM9607" },
269 { 291, "APQ8096" },
270 { 292, "MSM8998" },
271 { 293, "MSM8953" },
272 { 296, "MDM8207" },
273 { 297, "MDM9207" },
274 { 298, "MDM9307" },
275 { 299, "MDM9628" },
276 { 304, "APQ8053" },
277 { 305, "MSM8996SG" },
278 { 310, "MSM8996AU" },
279 { 311, "APQ8096AU" },
280 { 312, "APQ8096SG" },
281 { 317, "SDM660" },
282 { 318, "SDM630" },
283 { 319, "APQ8098" },
284 { 321, "SDM845" },
285 { 322, "MDM9206" },
286 { 323, "IPQ8074" },
287 { 324, "SDA660" },
288 { 325, "SDM658" },
289 { 326, "SDA658" },
290 { 327, "SDA630" },
291 { 338, "SDM450" },
292 { 341, "SDA845" },
293 { 342, "IPQ8072" },
294 { 343, "IPQ8076" },
295 { 344, "IPQ8078" },
296 { 345, "SDM636" },
297 { 346, "SDA636" },
298 { 349, "SDM632" },
299 { 350, "SDA632" },
300 { 351, "SDA450" },
301 { 356, "SM8250" },
302 { 375, "IPQ8070" },
303 { 376, "IPQ8071" },
304 { 389, "IPQ8072A" },
305 { 390, "IPQ8074A" },
306 { 391, "IPQ8076A" },
307 { 392, "IPQ8078A" },
308 { 394, "SM6125" },
309 { 395, "IPQ8070A" },
310 { 396, "IPQ8071A" },
311 { 402, "IPQ6018" },
312 { 403, "IPQ6028" },
313 { 421, "IPQ6000" },
314 { 422, "IPQ6010" },
315 { 425, "SC7180" },
316 { 453, "IPQ6005" },
317 { 455, "QRB5165" },
318 };
319
socinfo_machine(struct device * dev,unsigned int id)320 static const char *socinfo_machine(struct device *dev, unsigned int id)
321 {
322 int idx;
323
324 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) {
325 if (soc_id[idx].id == id)
326 return soc_id[idx].name;
327 }
328
329 return NULL;
330 }
331
332 #ifdef CONFIG_DEBUG_FS
333
334 #define QCOM_OPEN(name, _func) \
335 static int qcom_open_##name(struct inode *inode, struct file *file) \
336 { \
337 return single_open(file, _func, inode->i_private); \
338 } \
339 \
340 static const struct file_operations qcom_ ##name## _ops = { \
341 .open = qcom_open_##name, \
342 .read = seq_read, \
343 .llseek = seq_lseek, \
344 .release = single_release, \
345 }
346
347 #define DEBUGFS_ADD(info, name) \
348 debugfs_create_file(__stringify(name), 0444, \
349 qcom_socinfo->dbg_root, \
350 info, &qcom_ ##name## _ops)
351
352
qcom_show_build_id(struct seq_file * seq,void * p)353 static int qcom_show_build_id(struct seq_file *seq, void *p)
354 {
355 struct socinfo *socinfo = seq->private;
356
357 seq_printf(seq, "%s\n", socinfo->build_id);
358
359 return 0;
360 }
361
qcom_show_pmic_model(struct seq_file * seq,void * p)362 static int qcom_show_pmic_model(struct seq_file *seq, void *p)
363 {
364 struct socinfo *socinfo = seq->private;
365 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model));
366
367 if (model < 0)
368 return -EINVAL;
369
370 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
371 seq_printf(seq, "%s\n", pmic_models[model]);
372 else
373 seq_printf(seq, "unknown (%d)\n", model);
374
375 return 0;
376 }
377
qcom_show_pmic_model_array(struct seq_file * seq,void * p)378 static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
379 {
380 struct socinfo *socinfo = seq->private;
381 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
382 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
383 int i;
384 void *ptr = socinfo;
385
386 ptr += pmic_array_offset;
387
388 /* No need for bounds checking, it happened at socinfo_debugfs_init */
389 for (i = 0; i < num_pmics; i++) {
390 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
391 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
392
393 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
394 seq_printf(seq, "%s %u.%u\n", pmic_models[model],
395 SOCINFO_MAJOR(die_rev),
396 SOCINFO_MINOR(die_rev));
397 else
398 seq_printf(seq, "unknown (%d)\n", model);
399 }
400
401 return 0;
402 }
403
qcom_show_pmic_die_revision(struct seq_file * seq,void * p)404 static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
405 {
406 struct socinfo *socinfo = seq->private;
407
408 seq_printf(seq, "%u.%u\n",
409 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)),
410 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev)));
411
412 return 0;
413 }
414
qcom_show_chip_id(struct seq_file * seq,void * p)415 static int qcom_show_chip_id(struct seq_file *seq, void *p)
416 {
417 struct socinfo *socinfo = seq->private;
418
419 seq_printf(seq, "%s\n", socinfo->chip_id);
420
421 return 0;
422 }
423
424 QCOM_OPEN(build_id, qcom_show_build_id);
425 QCOM_OPEN(pmic_model, qcom_show_pmic_model);
426 QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
427 QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
428 QCOM_OPEN(chip_id, qcom_show_chip_id);
429
430 #define DEFINE_IMAGE_OPS(type) \
431 static int show_image_##type(struct seq_file *seq, void *p) \
432 { \
433 struct smem_image_version *image_version = seq->private; \
434 if (image_version->type[0] != '\0') \
435 seq_printf(seq, "%s\n", image_version->type); \
436 return 0; \
437 } \
438 static int open_image_##type(struct inode *inode, struct file *file) \
439 { \
440 return single_open(file, show_image_##type, inode->i_private); \
441 } \
442 \
443 static const struct file_operations qcom_image_##type##_ops = { \
444 .open = open_image_##type, \
445 .read = seq_read, \
446 .llseek = seq_lseek, \
447 .release = single_release, \
448 }
449
450 DEFINE_IMAGE_OPS(name);
451 DEFINE_IMAGE_OPS(variant);
452 DEFINE_IMAGE_OPS(oem);
453
socinfo_debugfs_init(struct qcom_socinfo * qcom_socinfo,struct socinfo * info,size_t info_size)454 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
455 struct socinfo *info, size_t info_size)
456 {
457 struct smem_image_version *versions;
458 struct dentry *dentry;
459 size_t size;
460 int i;
461 unsigned int num_pmics;
462 unsigned int pmic_array_offset;
463
464 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
465
466 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
467
468 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
469 &qcom_socinfo->info.fmt);
470
471 switch (qcom_socinfo->info.fmt) {
472 case SOCINFO_VERSION(0, 15):
473 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
474
475 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
476 &qcom_socinfo->info.nmodem_supported);
477 fallthrough;
478 case SOCINFO_VERSION(0, 14):
479 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
480 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
481 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
482 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
483
484 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
485 &qcom_socinfo->info.num_clusters);
486 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
487 &qcom_socinfo->info.ncluster_array_offset);
488 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
489 &qcom_socinfo->info.num_defective_parts);
490 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
491 &qcom_socinfo->info.ndefective_parts_array_offset);
492 fallthrough;
493 case SOCINFO_VERSION(0, 13):
494 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
495
496 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
497 &qcom_socinfo->info.nproduct_id);
498 DEBUGFS_ADD(info, chip_id);
499 fallthrough;
500 case SOCINFO_VERSION(0, 12):
501 qcom_socinfo->info.chip_family =
502 __le32_to_cpu(info->chip_family);
503 qcom_socinfo->info.raw_device_family =
504 __le32_to_cpu(info->raw_device_family);
505 qcom_socinfo->info.raw_device_num =
506 __le32_to_cpu(info->raw_device_num);
507
508 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
509 &qcom_socinfo->info.chip_family);
510 debugfs_create_x32("raw_device_family", 0444,
511 qcom_socinfo->dbg_root,
512 &qcom_socinfo->info.raw_device_family);
513 debugfs_create_x32("raw_device_number", 0444,
514 qcom_socinfo->dbg_root,
515 &qcom_socinfo->info.raw_device_num);
516 fallthrough;
517 case SOCINFO_VERSION(0, 11):
518 num_pmics = le32_to_cpu(info->num_pmics);
519 pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
520 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
521 DEBUGFS_ADD(info, pmic_model_array);
522 fallthrough;
523 case SOCINFO_VERSION(0, 10):
524 case SOCINFO_VERSION(0, 9):
525 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
526
527 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
528 &qcom_socinfo->info.foundry_id);
529 fallthrough;
530 case SOCINFO_VERSION(0, 8):
531 case SOCINFO_VERSION(0, 7):
532 DEBUGFS_ADD(info, pmic_model);
533 DEBUGFS_ADD(info, pmic_die_rev);
534 fallthrough;
535 case SOCINFO_VERSION(0, 6):
536 qcom_socinfo->info.hw_plat_subtype =
537 __le32_to_cpu(info->hw_plat_subtype);
538
539 debugfs_create_u32("hardware_platform_subtype", 0444,
540 qcom_socinfo->dbg_root,
541 &qcom_socinfo->info.hw_plat_subtype);
542 fallthrough;
543 case SOCINFO_VERSION(0, 5):
544 qcom_socinfo->info.accessory_chip =
545 __le32_to_cpu(info->accessory_chip);
546
547 debugfs_create_u32("accessory_chip", 0444,
548 qcom_socinfo->dbg_root,
549 &qcom_socinfo->info.accessory_chip);
550 fallthrough;
551 case SOCINFO_VERSION(0, 4):
552 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
553
554 debugfs_create_u32("platform_version", 0444,
555 qcom_socinfo->dbg_root,
556 &qcom_socinfo->info.plat_ver);
557 fallthrough;
558 case SOCINFO_VERSION(0, 3):
559 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
560
561 debugfs_create_u32("hardware_platform", 0444,
562 qcom_socinfo->dbg_root,
563 &qcom_socinfo->info.hw_plat);
564 fallthrough;
565 case SOCINFO_VERSION(0, 2):
566 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
567
568 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
569 &qcom_socinfo->info.raw_ver);
570 fallthrough;
571 case SOCINFO_VERSION(0, 1):
572 DEBUGFS_ADD(info, build_id);
573 break;
574 }
575
576 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
577 &size);
578
579 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
580 if (!socinfo_image_names[i])
581 continue;
582
583 dentry = debugfs_create_dir(socinfo_image_names[i],
584 qcom_socinfo->dbg_root);
585 debugfs_create_file("name", 0444, dentry, &versions[i],
586 &qcom_image_name_ops);
587 debugfs_create_file("variant", 0444, dentry, &versions[i],
588 &qcom_image_variant_ops);
589 debugfs_create_file("oem", 0444, dentry, &versions[i],
590 &qcom_image_oem_ops);
591 }
592 }
593
socinfo_debugfs_exit(struct qcom_socinfo * qcom_socinfo)594 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
595 {
596 debugfs_remove_recursive(qcom_socinfo->dbg_root);
597 }
598 #else
socinfo_debugfs_init(struct qcom_socinfo * qcom_socinfo,struct socinfo * info,size_t info_size)599 static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
600 struct socinfo *info, size_t info_size)
601 {
602 }
socinfo_debugfs_exit(struct qcom_socinfo * qcom_socinfo)603 static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
604 #endif /* CONFIG_DEBUG_FS */
605
qcom_socinfo_probe(struct platform_device * pdev)606 static int qcom_socinfo_probe(struct platform_device *pdev)
607 {
608 struct qcom_socinfo *qs;
609 struct socinfo *info;
610 size_t item_size;
611
612 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID,
613 &item_size);
614 if (IS_ERR(info)) {
615 dev_err(&pdev->dev, "Couldn't find socinfo\n");
616 return PTR_ERR(info);
617 }
618
619 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL);
620 if (!qs)
621 return -ENOMEM;
622
623 qs->attr.family = "Snapdragon";
624 qs->attr.machine = socinfo_machine(&pdev->dev,
625 le32_to_cpu(info->id));
626 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
627 le32_to_cpu(info->id));
628 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u",
629 SOCINFO_MAJOR(le32_to_cpu(info->ver)),
630 SOCINFO_MINOR(le32_to_cpu(info->ver)));
631 if (offsetof(struct socinfo, serial_num) <= item_size)
632 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL,
633 "%u",
634 le32_to_cpu(info->serial_num));
635
636 qs->soc_dev = soc_device_register(&qs->attr);
637 if (IS_ERR(qs->soc_dev))
638 return PTR_ERR(qs->soc_dev);
639
640 socinfo_debugfs_init(qs, info, item_size);
641
642 /* Feed the soc specific unique data into entropy pool */
643 add_device_randomness(info, item_size);
644
645 platform_set_drvdata(pdev, qs);
646
647 return 0;
648 }
649
qcom_socinfo_remove(struct platform_device * pdev)650 static int qcom_socinfo_remove(struct platform_device *pdev)
651 {
652 struct qcom_socinfo *qs = platform_get_drvdata(pdev);
653
654 soc_device_unregister(qs->soc_dev);
655
656 socinfo_debugfs_exit(qs);
657
658 return 0;
659 }
660
661 static struct platform_driver qcom_socinfo_driver = {
662 .probe = qcom_socinfo_probe,
663 .remove = qcom_socinfo_remove,
664 .driver = {
665 .name = "qcom-socinfo",
666 },
667 };
668
669 module_platform_driver(qcom_socinfo_driver);
670
671 MODULE_DESCRIPTION("Qualcomm SoCinfo driver");
672 MODULE_LICENSE("GPL v2");
673 MODULE_ALIAS("platform:qcom-socinfo");
674