1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ARM Generic Interrupt Controller (GIC) v3 specific defines 4 */ 5 6 #ifndef SELFTEST_KVM_GICV3_H 7 #define SELFTEST_KVM_GICV3_H 8 9 #include <asm/sysreg.h> 10 11 /* 12 * Distributor registers 13 */ 14 #define GICD_CTLR 0x0000 15 #define GICD_TYPER 0x0004 16 #define GICD_IGROUPR 0x0080 17 #define GICD_ISENABLER 0x0100 18 #define GICD_ICENABLER 0x0180 19 #define GICD_ICACTIVER 0x0380 20 #define GICD_IPRIORITYR 0x0400 21 22 /* 23 * The assumption is that the guest runs in a non-secure mode. 24 * The following bits of GICD_CTLR are defined accordingly. 25 */ 26 #define GICD_CTLR_RWP (1U << 31) 27 #define GICD_CTLR_nASSGIreq (1U << 8) 28 #define GICD_CTLR_ARE_NS (1U << 4) 29 #define GICD_CTLR_ENABLE_G1A (1U << 1) 30 #define GICD_CTLR_ENABLE_G1 (1U << 0) 31 32 #define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) 33 #define GICD_INT_DEF_PRI_X4 0xa0a0a0a0 34 35 /* 36 * Redistributor registers 37 */ 38 #define GICR_CTLR 0x000 39 #define GICR_WAKER 0x014 40 41 #define GICR_CTLR_RWP (1U << 3) 42 43 #define GICR_WAKER_ProcessorSleep (1U << 1) 44 #define GICR_WAKER_ChildrenAsleep (1U << 2) 45 46 /* 47 * Redistributor registers, offsets from SGI base 48 */ 49 #define GICR_IGROUPR0 GICD_IGROUPR 50 #define GICR_ISENABLER0 GICD_ISENABLER 51 #define GICR_ICENABLER0 GICD_ICENABLER 52 #define GICR_ICACTIVER0 GICD_ICACTIVER 53 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 54 55 /* CPU interface registers */ 56 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 57 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 58 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 59 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 60 #define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 61 62 #define ICC_PMR_DEF_PRIO 0xf0 63 64 #define ICC_SRE_EL1_SRE (1U << 0) 65 66 #define ICC_IGRPEN1_EL1_ENABLE (1U << 0) 67 68 #define GICV3_MAX_CPUS 512 69 70 #endif /* SELFTEST_KVM_GICV3_H */ 71