Lines Matching refs:DPLL
1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
52 - DPLL mode setting - defining any one or more of the following overrides
54 - ti,low-power-stop : DPLL supports low power stop mode, gating output
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
56 - ti,lock : DPLL locks in programmed rate
57 - ti,min-div : the minimum divisor to start from to round the DPLL
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
63 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean