Lines Matching refs:mcr
55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
73 mcr p15, 0, ip, c7, c10, 4 @ drain WB
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
101 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
170 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
173 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
212 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
213 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 mcr p15, 0, r0, c7, c10, 4 @ drain WB
233 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
239 mcr p15, 0, r0, c7, c10, 4 @ drain WB
264 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
268 mcr p15, 0, r0, c7, c10, 4 @ drain WB
284 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
289 mcr p15, 0, r0, c7, c10, 4 @ drain WB
304 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
311 mcr p15, 0, r0, c7, c10, 4 @ drain WB
341 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
346 mcr p15, 0, r0, c7, c10, 4 @ drain WB
365 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
371 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
372 mcr p15, 0, ip, c7, c10, 4 @ drain WB
373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
390 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
392 mcr p15, 0, r0, c7, c10, 4 @ drain WB
412 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
413 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
415 mcr p15, 0, r4, c13, c0, 0 @ PID
416 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
417 mcr p15, 0, r1, c2, c0, 0 @ TTB address
426 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
427 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
429 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
435 mcr p15, 7, r0, c15, c0, 0