Lines Matching refs:mcr
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
142 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
145 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
185 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
186 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
190 mcr p15, 0, r0, c7, c10, 4 @ drain WB
206 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
211 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
212 mcr p15, 0, r0, c7, c10, 4 @ drain WB
235 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
239 mcr p15, 0, r0, c7, c10, 4 @ drain WB
254 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
272 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
276 mcr p15, 0, r0, c7, c10, 4 @ drain WB
305 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
309 mcr p15, 0, r0, c7, c10, 4 @ drain WB
323 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
324 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
325 mcr p15, 0, ip, c7, c10, 4 @ drain WB
327 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
328 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
342 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
343 mcr p15, 0, r0, c7, c10, 4 @ drain WB
367 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
368 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
369 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
370 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
371 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
372 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
373 mcr p15, 0, r6, c13, c0, 0 @ PID
374 mcr p15, 0, r7, c3, c0, 0 @ domain ID
376 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
377 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
387 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
388 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
390 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer