Lines Matching refs:mcr
69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
233 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
239 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
240 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
255 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
260 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
261 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
262 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
287 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
300 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
304 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
317 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
321 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
369 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
370 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
371 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
439 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
440 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
441 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
442 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
443 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
444 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
445 mcr p15, 0, r6, c13, c0, 0 @ PID
446 mcr p15, 0, r7, c3, c0, 0 @ domain ID
448 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
449 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
459 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
460 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
461 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
462 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
464 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
467 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
472 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg