Lines Matching refs:x1
53 __check_hvhe .LnVHE_\@, x1
61 mrs x1, id_aa64dfr0_el1
62 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
72 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
88 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4
105 mrs x1, id_aa64mmfr1_el1
106 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
141 mrs x1, mpidr_el1
143 msr vmpidr_el2, x1
148 __check_hvhe .LnVHE_\@, x1
160 mrs x1, id_aa64mmfr0_el1
161 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
162 cbz x1, .Lskip_fgt_\@
165 mrs x1, id_aa64dfr0_el1
166 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
167 cmp x1, #3
177 mrs x1, id_aa64pfr1_el1
178 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
179 cbz x1, .Lskip_debug_fgt_\@
186 mrs_s x1, SYS_ID_AA64MMFR3_EL1
187 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
188 cbz x1, .Lskip_pie_fgt_\@
195 mrs_s x1, SYS_ID_AA64MMFR3_EL1
196 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4
197 cbz x1, .Lskip_poe_fgt_\@
207 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
208 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
209 cbz x1, .Lskip_amu_fgt_\@
284 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2
287 __check_hvhe .Lcptr_nvhe_\@, x1
301 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
302 msr_s SYS_ZCR_EL2, x1 // length for EL1.
305 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2
308 __check_hvhe .Lcptr_nvhe_sme_\@, x1
323 mrs x1, sctlr_el2
324 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
325 msr sctlr_el2, x1
331 mrs_s x1, SYS_ID_AA64SMFR0_EL1
332 …erride id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2
339 mrs_s x1, SYS_ID_AA64SMFR0_EL1
340 …erride id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2
348 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
349 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
350 cbz x1, .Lskip_sme_\@