Lines Matching refs:val
76 u32 val = 0; in host_ss_rst_clr() local
78 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
79 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
80 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
82 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in host_ss_rst_clr()
87 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_37xx() local
89 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_37xx()
97 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_40xx() local
99 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_40xx()
115 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_37xx() local
117 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qacceptn_check_37xx()
125 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_40xx() local
127 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qacceptn_check_40xx()
143 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_37xx() local
145 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qdeny_check_37xx()
153 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_40xx() local
155 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qdeny_check_40xx()
171 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_37xx() local
173 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in top_noc_qrenqn_check_37xx()
174 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qrenqn_check_37xx()
182 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_40xx() local
184 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in top_noc_qrenqn_check_40xx()
185 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qrenqn_check_40xx()
233 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN); in idle_gen_drive_37xx() local
236 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
238 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
240 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val); in idle_gen_drive_37xx()
245 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); in idle_gen_drive_40xx() local
248 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
250 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
252 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); in idle_gen_drive_40xx()
273 u32 val, post, status; in pwr_island_delay_set_50xx() local
283 val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY); in pwr_island_delay_set_50xx()
284 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val); in pwr_island_delay_set_50xx()
285 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val); in pwr_island_delay_set_50xx()
287 val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY); in pwr_island_delay_set_50xx()
288 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val); in pwr_island_delay_set_50xx()
289 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val); in pwr_island_delay_set_50xx()
294 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); in pwr_island_trickle_drive_37xx() local
297 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in pwr_island_trickle_drive_37xx()
299 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in pwr_island_trickle_drive_37xx()
301 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in pwr_island_trickle_drive_37xx()
306 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); in pwr_island_trickle_drive_40xx() local
309 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); in pwr_island_trickle_drive_40xx()
311 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); in pwr_island_trickle_drive_40xx()
313 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in pwr_island_trickle_drive_40xx()
321 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); in pwr_island_drive_37xx() local
324 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); in pwr_island_drive_37xx()
326 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); in pwr_island_drive_37xx()
328 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in pwr_island_drive_37xx()
336 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); in pwr_island_drive_40xx() local
339 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in pwr_island_drive_40xx()
341 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in pwr_island_drive_40xx()
343 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in pwr_island_drive_40xx()
372 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); in pwr_island_isolation_drive_37xx() local
375 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()
377 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()
379 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_37xx()
384 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); in pwr_island_isolation_drive_40xx() local
387 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); in pwr_island_isolation_drive_40xx()
389 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); in pwr_island_isolation_drive_40xx()
391 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_40xx()
409 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); in host_ss_clk_drive_37xx() local
412 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in host_ss_clk_drive_37xx()
413 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in host_ss_clk_drive_37xx()
414 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in host_ss_clk_drive_37xx()
416 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in host_ss_clk_drive_37xx()
417 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in host_ss_clk_drive_37xx()
418 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in host_ss_clk_drive_37xx()
421 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); in host_ss_clk_drive_37xx()
426 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); in host_ss_clk_drive_40xx() local
429 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
430 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
431 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
433 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
434 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
435 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
438 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); in host_ss_clk_drive_40xx()
456 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); in host_ss_rst_drive_37xx() local
459 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); in host_ss_rst_drive_37xx()
460 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); in host_ss_rst_drive_37xx()
461 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); in host_ss_rst_drive_37xx()
463 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); in host_ss_rst_drive_37xx()
464 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); in host_ss_rst_drive_37xx()
465 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); in host_ss_rst_drive_37xx()
468 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); in host_ss_rst_drive_37xx()
473 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); in host_ss_rst_drive_40xx() local
476 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
477 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in host_ss_rst_drive_40xx()
478 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in host_ss_rst_drive_40xx()
480 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
481 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in host_ss_rst_drive_40xx()
482 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in host_ss_rst_drive_40xx()
485 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); in host_ss_rst_drive_40xx()
503 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_top_socmmio_drive_37xx() local
506 val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
508 val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
509 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
514 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_top_socmmio_drive_40xx() local
517 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
519 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
520 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
552 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qreqn_drive_40xx() local
555 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
556 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_40xx()
558 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
559 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_40xx()
562 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); in top_noc_qreqn_drive_40xx()
567 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qreqn_drive_37xx() local
570 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_37xx()
571 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_37xx()
573 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_37xx()
574 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_37xx()
577 REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val); in top_noc_qreqn_drive_37xx()
595 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); in top_noc_qacceptn_check_37xx() local
597 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in top_noc_qacceptn_check_37xx()
598 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qacceptn_check_37xx()
606 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); in top_noc_qacceptn_check_40xx() local
608 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in top_noc_qacceptn_check_40xx()
609 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qacceptn_check_40xx()
625 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); in top_noc_qdeny_check_37xx() local
627 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in top_noc_qdeny_check_37xx()
628 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qdeny_check_37xx()
636 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); in top_noc_qdeny_check_40xx() local
638 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in top_noc_qdeny_check_40xx()
639 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qdeny_check_40xx()
679 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); in dpu_active_drive_37xx() local
682 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); in dpu_active_drive_37xx()
684 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); in dpu_active_drive_37xx()
686 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); in dpu_active_drive_37xx()
730 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); in ivpu_hw_ip_snoop_disable_37xx() local
732 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val); in ivpu_hw_ip_snoop_disable_37xx()
733 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_37xx()
736 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_37xx()
738 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_37xx()
740 REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val); in ivpu_hw_ip_snoop_disable_37xx()
745 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); in ivpu_hw_ip_snoop_disable_40xx() local
747 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val); in ivpu_hw_ip_snoop_disable_40xx()
748 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_40xx()
751 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_40xx()
753 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_40xx()
755 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val); in ivpu_hw_ip_snoop_disable_40xx()
768 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); in ivpu_hw_ip_tbu_mmu_enable_37xx() local
770 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
771 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
772 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
773 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
775 REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
780 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); in ivpu_hw_ip_tbu_mmu_enable_40xx() local
782 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
783 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
784 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
785 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
786 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
787 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
789 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
802 u32 val; in soc_cpu_boot_37xx() local
804 val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC); in soc_cpu_boot_37xx()
805 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val); in soc_cpu_boot_37xx()
807 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val); in soc_cpu_boot_37xx()
808 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in soc_cpu_boot_37xx()
810 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); in soc_cpu_boot_37xx()
811 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in soc_cpu_boot_37xx()
813 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); in soc_cpu_boot_37xx()
814 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in soc_cpu_boot_37xx()
816 val = vdev->fw->entry_point >> 9; in soc_cpu_boot_37xx()
817 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); in soc_cpu_boot_37xx()
819 val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val); in soc_cpu_boot_37xx()
820 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); in soc_cpu_boot_37xx()
830 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN); in cpu_noc_qacceptn_check_40xx() local
832 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val)) in cpu_noc_qacceptn_check_40xx()
840 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY); in cpu_noc_qdeny_check_40xx() local
842 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val)) in cpu_noc_qdeny_check_40xx()
850 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN); in cpu_noc_top_mmio_drive_40xx() local
853 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); in cpu_noc_top_mmio_drive_40xx()
855 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); in cpu_noc_top_mmio_drive_40xx()
856 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val); in cpu_noc_top_mmio_drive_40xx()
886 u32 val; in soc_cpu_boot_40xx() local
899 val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO); in soc_cpu_boot_40xx()
900 val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val); in soc_cpu_boot_40xx()
901 REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val); in soc_cpu_boot_40xx()
919 u32 val; in wdt_disable_37xx() local
930 val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG); in wdt_disable_37xx()
931 val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); in wdt_disable_37xx()
932 REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val); in wdt_disable_37xx()
937 u32 val; in wdt_disable_40xx() local
945 val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG); in wdt_disable_40xx()
946 val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); in wdt_disable_40xx()
947 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val); in wdt_disable_40xx()
1142 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); in db_set_37xx() local
1144 REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); in db_set_37xx()
1150 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); in db_set_40xx() local
1152 REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); in db_set_40xx()