Lines Matching refs:chan
232 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; member
235 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) in stm32_dma_get_dev() argument
237 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
243 return container_of(c, struct stm32_dma_chan, vchan.chan); in to_stm32_dma_chan()
251 static struct device *chan2dev(struct stm32_dma_chan *chan) in chan2dev() argument
253 return &chan->vchan.chan.dev->device; in chan2dev()
266 static int stm32_dma_get_width(struct stm32_dma_chan *chan, in stm32_dma_get_width() argument
277 dev_err(chan2dev(chan), "Dma bus width not supported\n"); in stm32_dma_get_width()
364 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) in stm32_dma_get_burst() argument
377 dev_err(chan2dev(chan), "Dma burst size not supported\n"); in stm32_dma_get_burst()
382 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, in stm32_dma_set_fifo_config() argument
385 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
386 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
390 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
393 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
400 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_slave_config() local
402 memcpy(&chan->dma_sconfig, config, sizeof(*config)); in stm32_dma_slave_config()
406 config->peripheral_config = &chan->mdma_config; in stm32_dma_slave_config()
407 config->peripheral_size = sizeof(chan->mdma_config); in stm32_dma_slave_config()
408 chan->trig_mdma = true; in stm32_dma_slave_config()
411 chan->config_init = true; in stm32_dma_slave_config()
416 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) in stm32_dma_irq_status() argument
418 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_status()
426 dma_isr = stm32_dma_read(dmadev, STM32_DMA_ISR(chan->id)); in stm32_dma_irq_status()
427 flags = dma_isr >> STM32_DMA_FLAGS_SHIFT(chan->id); in stm32_dma_irq_status()
432 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) in stm32_dma_irq_clear() argument
434 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_clear()
442 dma_ifcr = flags << STM32_DMA_FLAGS_SHIFT(chan->id); in stm32_dma_irq_clear()
444 stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr); in stm32_dma_irq_clear()
447 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) in stm32_dma_disable_chan() argument
449 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_disable_chan()
452 id = chan->id; in stm32_dma_disable_chan()
468 static void stm32_dma_stop(struct stm32_dma_chan *chan) in stm32_dma_stop() argument
470 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_stop()
475 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
477 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
478 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_stop()
480 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
483 ret = stm32_dma_disable_chan(chan); in stm32_dma_stop()
488 status = stm32_dma_irq_status(chan); in stm32_dma_stop()
490 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", in stm32_dma_stop()
492 stm32_dma_irq_clear(chan, status); in stm32_dma_stop()
495 chan->busy = false; in stm32_dma_stop()
496 chan->status = DMA_COMPLETE; in stm32_dma_stop()
501 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_terminate_all() local
505 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
507 if (chan->desc) { in stm32_dma_terminate_all()
508 dma_cookie_complete(&chan->desc->vdesc.tx); in stm32_dma_terminate_all()
509 vchan_terminate_vdesc(&chan->desc->vdesc); in stm32_dma_terminate_all()
510 if (chan->busy) in stm32_dma_terminate_all()
511 stm32_dma_stop(chan); in stm32_dma_terminate_all()
512 chan->desc = NULL; in stm32_dma_terminate_all()
515 vchan_get_all_descriptors(&chan->vchan, &head); in stm32_dma_terminate_all()
516 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
517 vchan_dma_desc_free_list(&chan->vchan, &head); in stm32_dma_terminate_all()
524 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_synchronize() local
526 vchan_synchronize(&chan->vchan); in stm32_dma_synchronize()
529 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) in stm32_dma_dump_reg() argument
531 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_dump_reg()
532 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg()
533 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_dump_reg()
534 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); in stm32_dma_dump_reg()
535 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); in stm32_dma_dump_reg()
536 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); in stm32_dma_dump_reg()
537 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_dump_reg()
539 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); in stm32_dma_dump_reg()
540 dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); in stm32_dma_dump_reg()
541 dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); in stm32_dma_dump_reg()
542 dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); in stm32_dma_dump_reg()
543 dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); in stm32_dma_dump_reg()
544 dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); in stm32_dma_dump_reg()
547 static void stm32_dma_sg_inc(struct stm32_dma_chan *chan) in stm32_dma_sg_inc() argument
549 chan->next_sg++; in stm32_dma_sg_inc()
550 if (chan->desc->cyclic && (chan->next_sg == chan->desc->num_sgs)) in stm32_dma_sg_inc()
551 chan->next_sg = 0; in stm32_dma_sg_inc()
554 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
556 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) in stm32_dma_start_transfer() argument
558 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_start_transfer()
565 ret = stm32_dma_disable_chan(chan); in stm32_dma_start_transfer()
569 if (!chan->desc) { in stm32_dma_start_transfer()
570 vdesc = vchan_next_desc(&chan->vchan); in stm32_dma_start_transfer()
576 chan->desc = to_stm32_dma_desc(vdesc); in stm32_dma_start_transfer()
577 chan->next_sg = 0; in stm32_dma_start_transfer()
580 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_start_transfer()
581 chan->next_sg = 0; in stm32_dma_start_transfer()
583 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_start_transfer()
587 if (chan->trig_mdma && chan->dma_sconfig.direction != DMA_MEM_TO_DEV) in stm32_dma_start_transfer()
591 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
592 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
593 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
594 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
595 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
596 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
598 stm32_dma_sg_inc(chan); in stm32_dma_start_transfer()
601 status = stm32_dma_irq_status(chan); in stm32_dma_start_transfer()
603 stm32_dma_irq_clear(chan, status); in stm32_dma_start_transfer()
605 if (chan->desc->cyclic) in stm32_dma_start_transfer()
606 stm32_dma_configure_next_sg(chan); in stm32_dma_start_transfer()
608 stm32_dma_dump_reg(chan); in stm32_dma_start_transfer()
611 chan->busy = true; in stm32_dma_start_transfer()
612 chan->status = DMA_IN_PROGRESS; in stm32_dma_start_transfer()
614 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
616 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); in stm32_dma_start_transfer()
619 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) in stm32_dma_configure_next_sg() argument
621 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_configure_next_sg()
625 id = chan->id; in stm32_dma_configure_next_sg()
628 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_configure_next_sg()
633 dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", in stm32_dma_configure_next_sg()
638 dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", in stm32_dma_configure_next_sg()
643 static void stm32_dma_handle_chan_paused(struct stm32_dma_chan *chan) in stm32_dma_handle_chan_paused() argument
645 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_handle_chan_paused()
652 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_handle_chan_paused()
658 if (chan->desc && chan->desc->cyclic) { in stm32_dma_handle_chan_paused()
659 if (chan->desc->num_sgs == 1) in stm32_dma_handle_chan_paused()
664 chan->chan_reg.dma_scr = dma_scr; in stm32_dma_handle_chan_paused()
670 if (chan->desc && chan->desc->cyclic) { in stm32_dma_handle_chan_paused()
672 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_handle_chan_paused()
675 chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_handle_chan_paused()
677 chan->status = DMA_PAUSED; in stm32_dma_handle_chan_paused()
679 dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); in stm32_dma_handle_chan_paused()
682 static void stm32_dma_post_resume_reconfigure(struct stm32_dma_chan *chan) in stm32_dma_post_resume_reconfigure() argument
684 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_post_resume_reconfigure()
688 id = chan->id; in stm32_dma_post_resume_reconfigure()
692 status = stm32_dma_irq_status(chan); in stm32_dma_post_resume_reconfigure()
694 stm32_dma_irq_clear(chan, status); in stm32_dma_post_resume_reconfigure()
696 if (!chan->next_sg) in stm32_dma_post_resume_reconfigure()
697 sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1]; in stm32_dma_post_resume_reconfigure()
699 sg_req = &chan->desc->sg_req[chan->next_sg - 1]; in stm32_dma_post_resume_reconfigure()
702 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr); in stm32_dma_post_resume_reconfigure()
712 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) { in stm32_dma_post_resume_reconfigure()
715 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT) in stm32_dma_post_resume_reconfigure()
719 } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) { in stm32_dma_post_resume_reconfigure()
722 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_post_resume_reconfigure()
724 stm32_dma_configure_next_sg(chan); in stm32_dma_post_resume_reconfigure()
726 stm32_dma_dump_reg(chan); in stm32_dma_post_resume_reconfigure()
729 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_post_resume_reconfigure()
731 dev_dbg(chan2dev(chan), "vchan %pK: reconfigured after pause/resume\n", &chan->vchan); in stm32_dma_post_resume_reconfigure()
734 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr) in stm32_dma_handle_chan_done() argument
736 if (!chan->desc) in stm32_dma_handle_chan_done()
739 if (chan->desc->cyclic) { in stm32_dma_handle_chan_done()
740 vchan_cyclic_callback(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
741 if (chan->trig_mdma) in stm32_dma_handle_chan_done()
743 stm32_dma_sg_inc(chan); in stm32_dma_handle_chan_done()
746 stm32_dma_post_resume_reconfigure(chan); in stm32_dma_handle_chan_done()
748 stm32_dma_configure_next_sg(chan); in stm32_dma_handle_chan_done()
750 chan->busy = false; in stm32_dma_handle_chan_done()
751 chan->status = DMA_COMPLETE; in stm32_dma_handle_chan_done()
752 if (chan->next_sg == chan->desc->num_sgs) { in stm32_dma_handle_chan_done()
753 vchan_cookie_complete(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
754 chan->desc = NULL; in stm32_dma_handle_chan_done()
756 stm32_dma_start_transfer(chan); in stm32_dma_handle_chan_done()
762 struct stm32_dma_chan *chan = devid; in stm32_dma_chan_irq() local
763 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_chan_irq()
766 spin_lock(&chan->vchan.lock); in stm32_dma_chan_irq()
768 status = stm32_dma_irq_status(chan); in stm32_dma_chan_irq()
769 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
770 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_chan_irq()
773 stm32_dma_irq_clear(chan, STM32_DMA_FEI); in stm32_dma_chan_irq()
778 dev_err(chan2dev(chan), "FIFO Error\n"); in stm32_dma_chan_irq()
780 dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); in stm32_dma_chan_irq()
784 stm32_dma_irq_clear(chan, STM32_DMA_DMEI); in stm32_dma_chan_irq()
787 dev_dbg(chan2dev(chan), "Direct mode overrun\n"); in stm32_dma_chan_irq()
791 stm32_dma_irq_clear(chan, STM32_DMA_TCI); in stm32_dma_chan_irq()
793 if (chan->status != DMA_PAUSED) in stm32_dma_chan_irq()
794 stm32_dma_handle_chan_done(chan, scr); in stm32_dma_chan_irq()
800 stm32_dma_irq_clear(chan, STM32_DMA_HTI); in stm32_dma_chan_irq()
805 stm32_dma_irq_clear(chan, status); in stm32_dma_chan_irq()
806 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); in stm32_dma_chan_irq()
808 dev_err(chan2dev(chan), "chan disabled by HW\n"); in stm32_dma_chan_irq()
811 spin_unlock(&chan->vchan.lock); in stm32_dma_chan_irq()
818 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_issue_pending() local
821 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
822 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { in stm32_dma_issue_pending()
823 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); in stm32_dma_issue_pending()
824 stm32_dma_start_transfer(chan); in stm32_dma_issue_pending()
827 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
832 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_pause() local
836 if (chan->status != DMA_IN_PROGRESS) in stm32_dma_pause()
839 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_pause()
841 ret = stm32_dma_disable_chan(chan); in stm32_dma_pause()
843 stm32_dma_handle_chan_paused(chan); in stm32_dma_pause()
845 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_pause()
852 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_resume() local
853 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_resume()
854 struct stm32_dma_chan_reg chan_reg = chan->chan_reg; in stm32_dma_resume()
855 u32 id = chan->id, scr, ndtr, offset, spar, sm0ar, sm1ar; in stm32_dma_resume()
859 if (chan->status != DMA_PAUSED) in stm32_dma_resume()
866 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_resume()
869 if (!chan->next_sg) in stm32_dma_resume()
870 sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1]; in stm32_dma_resume()
872 sg_req = &chan->desc->sg_req[chan->next_sg - 1]; in stm32_dma_resume()
914 stm32_dma_configure_next_sg(chan); in stm32_dma_resume()
916 stm32_dma_dump_reg(chan); in stm32_dma_resume()
919 chan->status = DMA_IN_PROGRESS; in stm32_dma_resume()
923 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_resume()
925 dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan); in stm32_dma_resume()
930 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, in stm32_dma_set_xfer_param() argument
941 src_addr_width = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
942 dst_addr_width = chan->dma_sconfig.dst_addr_width; in stm32_dma_set_xfer_param()
943 src_maxburst = chan->dma_sconfig.src_maxburst; in stm32_dma_set_xfer_param()
944 dst_maxburst = chan->dma_sconfig.dst_maxburst; in stm32_dma_set_xfer_param()
945 fifoth = chan->threshold; in stm32_dma_set_xfer_param()
950 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); in stm32_dma_set_xfer_param()
960 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); in stm32_dma_set_xfer_param()
967 chan->mem_width = src_addr_width; in stm32_dma_set_xfer_param()
968 src_bus_width = stm32_dma_get_width(chan, src_addr_width); in stm32_dma_set_xfer_param()
984 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); in stm32_dma_set_xfer_param()
995 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
997 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth); in stm32_dma_set_xfer_param()
1000 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; in stm32_dma_set_xfer_param()
1006 src_bus_width = stm32_dma_get_width(chan, src_addr_width); in stm32_dma_set_xfer_param()
1015 chan->mem_burst = src_best_burst; in stm32_dma_set_xfer_param()
1016 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); in stm32_dma_set_xfer_param()
1023 chan->mem_width = dst_addr_width; in stm32_dma_set_xfer_param()
1024 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); in stm32_dma_set_xfer_param()
1040 chan->mem_burst = dst_best_burst; in stm32_dma_set_xfer_param()
1041 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); in stm32_dma_set_xfer_param()
1052 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
1054 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth); in stm32_dma_set_xfer_param()
1057 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; in stm32_dma_set_xfer_param()
1058 *buswidth = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
1062 dev_err(chan2dev(chan), "Dma direction is not supported\n"); in stm32_dma_set_xfer_param()
1066 stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); in stm32_dma_set_xfer_param()
1069 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | in stm32_dma_set_xfer_param()
1072 chan->chan_reg.dma_scr |= dma_scr; in stm32_dma_set_xfer_param()
1087 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_slave_sg() local
1094 if (!chan->config_init) { in stm32_dma_prep_slave_sg()
1095 dev_err(chan2dev(chan), "dma channel is not configured\n"); in stm32_dma_prep_slave_sg()
1100 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); in stm32_dma_prep_slave_sg()
1110 if (chan->dma_sconfig.device_fc) in stm32_dma_prep_slave_sg()
1111 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
1113 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
1116 if (chan->trig_mdma && sg_len > 1) { in stm32_dma_prep_slave_sg()
1117 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_slave_sg()
1118 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT; in stm32_dma_prep_slave_sg()
1122 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, in stm32_dma_prep_slave_sg()
1132 dev_err(chan2dev(chan), "nb items not supported\n"); in stm32_dma_prep_slave_sg()
1137 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_slave_sg()
1138 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_slave_sg()
1139 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_slave_sg()
1142 if (chan->trig_mdma) in stm32_dma_prep_slave_sg()
1148 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_slave_sg()
1160 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_dma_cyclic() local
1167 dev_err(chan2dev(chan), "Invalid buffer/period len\n"); in stm32_dma_prep_dma_cyclic()
1171 if (!chan->config_init) { in stm32_dma_prep_dma_cyclic()
1172 dev_err(chan2dev(chan), "dma channel is not configured\n"); in stm32_dma_prep_dma_cyclic()
1177 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); in stm32_dma_prep_dma_cyclic()
1187 if (chan->busy) { in stm32_dma_prep_dma_cyclic()
1188 dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); in stm32_dma_prep_dma_cyclic()
1192 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len, in stm32_dma_prep_dma_cyclic()
1199 dev_err(chan2dev(chan), "number of items not supported\n"); in stm32_dma_prep_dma_cyclic()
1205 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_prep_dma_cyclic()
1207 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_dma_cyclic()
1208 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT; in stm32_dma_prep_dma_cyclic()
1212 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_dma_cyclic()
1225 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_dma_cyclic()
1226 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_dma_cyclic()
1227 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_dma_cyclic()
1230 if (chan->trig_mdma) in stm32_dma_prep_dma_cyclic()
1233 if (!chan->trig_mdma) in stm32_dma_prep_dma_cyclic()
1238 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_cyclic()
1245 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_dma_memcpy() local
1258 threshold = chan->threshold; in stm32_dma_prep_dma_memcpy()
1268 dma_burst = stm32_dma_get_burst(chan, best_burst); in stm32_dma_prep_dma_memcpy()
1292 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_memcpy()
1295 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) in stm32_dma_get_remaining_bytes() argument
1298 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_get_remaining_bytes()
1300 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
1302 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_get_remaining_bytes()
1319 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) in stm32_dma_is_current_sg() argument
1321 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_is_current_sg()
1325 id = chan->id; in stm32_dma_is_current_sg()
1332 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_is_current_sg()
1355 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, in stm32_dma_desc_residue() argument
1362 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_desc_residue()
1390 residue = stm32_dma_get_remaining_bytes(chan); in stm32_dma_desc_residue()
1392 if ((chan->desc->cyclic || chan->trig_mdma) && !stm32_dma_is_current_sg(chan)) { in stm32_dma_desc_residue()
1394 if (n_sg == chan->desc->num_sgs) in stm32_dma_desc_residue()
1396 if (!chan->trig_mdma) in stm32_dma_desc_residue()
1407 if ((!chan->desc->cyclic && !chan->trig_mdma) || n_sg != 0) in stm32_dma_desc_residue()
1411 if (!chan->mem_burst) in stm32_dma_desc_residue()
1414 burst_size = chan->mem_burst * chan->mem_width; in stm32_dma_desc_residue()
1426 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_tx_status() local
1436 status = chan->status; in stm32_dma_tx_status()
1441 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1442 vdesc = vchan_find_desc(&chan->vchan, cookie); in stm32_dma_tx_status()
1443 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) in stm32_dma_tx_status()
1444 residue = stm32_dma_desc_residue(chan, chan->desc, in stm32_dma_tx_status()
1445 chan->next_sg); in stm32_dma_tx_status()
1447 residue = stm32_dma_desc_residue(chan, in stm32_dma_tx_status()
1451 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1458 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_alloc_chan_resources() local
1459 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_alloc_chan_resources()
1462 chan->config_init = false; in stm32_dma_alloc_chan_resources()
1468 ret = stm32_dma_disable_chan(chan); in stm32_dma_alloc_chan_resources()
1477 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_free_chan_resources() local
1478 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_free_chan_resources()
1481 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); in stm32_dma_free_chan_resources()
1483 if (chan->busy) { in stm32_dma_free_chan_resources()
1484 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1485 stm32_dma_stop(chan); in stm32_dma_free_chan_resources()
1486 chan->desc = NULL; in stm32_dma_free_chan_resources()
1487 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1493 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_free_chan_resources()
1494 chan->threshold = 0; in stm32_dma_free_chan_resources()
1502 static void stm32_dma_set_config(struct stm32_dma_chan *chan, in stm32_dma_set_config() argument
1505 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_set_config()
1507 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; in stm32_dma_set_config()
1508 chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line); in stm32_dma_set_config()
1511 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; in stm32_dma_set_config()
1513 chan->threshold = FIELD_GET(STM32_DMA_THRESHOLD_FTR_MASK, cfg->features); in stm32_dma_set_config()
1515 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; in stm32_dma_set_config()
1517 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; in stm32_dma_set_config()
1518 chan->mdma_config.stream_id = FIELD_GET(STM32_DMA_MDMA_STREAM_ID_MASK, cfg->features); in stm32_dma_set_config()
1527 struct stm32_dma_chan *chan; in stm32_dma_of_xlate() local
1546 chan = &dmadev->chan[cfg.channel_id]; in stm32_dma_of_xlate()
1548 c = dma_get_slave_channel(&chan->vchan.chan); in stm32_dma_of_xlate()
1554 stm32_dma_set_config(chan, &cfg); in stm32_dma_of_xlate()
1567 struct stm32_dma_chan *chan; in stm32_dma_probe() local
1646 chan = &dmadev->chan[i]; in stm32_dma_probe()
1647 chan->id = i; in stm32_dma_probe()
1648 chan->vchan.desc_free = stm32_dma_desc_free; in stm32_dma_probe()
1649 vchan_init(&chan->vchan, dd); in stm32_dma_probe()
1651 chan->mdma_config.ifcr = res->start; in stm32_dma_probe()
1652 chan->mdma_config.ifcr += STM32_DMA_IFCR(chan->id); in stm32_dma_probe()
1654 chan->mdma_config.tcf = STM32_DMA_TCI; in stm32_dma_probe()
1655 chan->mdma_config.tcf <<= STM32_DMA_FLAGS_SHIFT(chan->id); in stm32_dma_probe()
1663 chan = &dmadev->chan[i]; in stm32_dma_probe()
1667 chan->irq = ret; in stm32_dma_probe()
1669 ret = devm_request_irq(&pdev->dev, chan->irq, in stm32_dma_probe()
1671 dev_name(chan2dev(chan)), chan); in stm32_dma_probe()