Lines Matching refs:chan
453 void (*start_transfer)(struct xilinx_dma_chan *chan);
454 int (*stop_transfer)(struct xilinx_dma_chan *chan);
509 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; member
526 #define to_xilinx_chan(chan) \ argument
527 container_of(chan, struct xilinx_dma_chan, common)
530 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ argument
531 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
535 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) in dma_read() argument
537 return ioread32(chan->xdev->regs + reg); in dma_read()
540 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) in dma_write() argument
542 iowrite32(value, chan->xdev->regs + reg); in dma_write()
545 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, in vdma_desc_write() argument
548 dma_write(chan, chan->desc_offset + reg, value); in vdma_desc_write()
551 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) in dma_ctrl_read() argument
553 return dma_read(chan, chan->ctrl_offset + reg); in dma_ctrl_read()
556 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, in dma_ctrl_write() argument
559 dma_write(chan, chan->ctrl_offset + reg, value); in dma_ctrl_write()
562 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, in dma_ctrl_clr() argument
565 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); in dma_ctrl_clr()
568 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, in dma_ctrl_set() argument
571 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); in dma_ctrl_set()
585 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, in vdma_desc_write_64() argument
589 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); in vdma_desc_write_64()
592 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); in vdma_desc_write_64()
595 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) in dma_writeq() argument
597 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); in dma_writeq()
600 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, in xilinx_write() argument
603 if (chan->ext_addr) in xilinx_write()
604 dma_writeq(chan, reg, addr); in xilinx_write()
606 dma_ctrl_write(chan, reg, addr); in xilinx_write()
609 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, in xilinx_axidma_buf() argument
614 if (chan->ext_addr) { in xilinx_axidma_buf()
623 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, in xilinx_aximcdma_buf() argument
627 if (chan->ext_addr) { in xilinx_aximcdma_buf()
669 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_vdma_alloc_tx_segment() argument
674 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_vdma_alloc_tx_segment()
690 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_cdma_alloc_tx_segment() argument
695 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_cdma_alloc_tx_segment()
711 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_axidma_alloc_tx_segment() argument
716 spin_lock_irqsave(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
717 if (!list_empty(&chan->free_seg_list)) { in xilinx_axidma_alloc_tx_segment()
718 segment = list_first_entry(&chan->free_seg_list, in xilinx_axidma_alloc_tx_segment()
723 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
726 dev_dbg(chan->dev, "Could not find free tx segment\n"); in xilinx_axidma_alloc_tx_segment()
738 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_aximcdma_alloc_tx_segment() argument
743 spin_lock_irqsave(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
744 if (!list_empty(&chan->free_seg_list)) { in xilinx_aximcdma_alloc_tx_segment()
745 segment = list_first_entry(&chan->free_seg_list, in xilinx_aximcdma_alloc_tx_segment()
750 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
782 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_dma_free_tx_segment() argument
787 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_dma_free_tx_segment()
795 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_mcdma_free_tx_segment() argument
801 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_mcdma_free_tx_segment()
809 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_cdma_free_tx_segment() argument
812 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_cdma_free_tx_segment()
820 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_vdma_free_tx_segment() argument
823 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_vdma_free_tx_segment()
833 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) in xilinx_dma_alloc_tx_descriptor() argument
852 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, in xilinx_dma_free_tx_descriptor() argument
863 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_free_tx_descriptor()
866 xilinx_vdma_free_tx_segment(chan, segment); in xilinx_dma_free_tx_descriptor()
868 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_free_tx_descriptor()
872 xilinx_cdma_free_tx_segment(chan, cdma_segment); in xilinx_dma_free_tx_descriptor()
874 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_tx_descriptor()
878 xilinx_dma_free_tx_segment(chan, axidma_segment); in xilinx_dma_free_tx_descriptor()
884 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); in xilinx_dma_free_tx_descriptor()
898 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, in xilinx_dma_free_desc_list() argument
905 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_free_desc_list()
913 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) in xilinx_dma_free_descriptors() argument
917 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_descriptors()
919 xilinx_dma_free_desc_list(chan, &chan->pending_list); in xilinx_dma_free_descriptors()
920 xilinx_dma_free_desc_list(chan, &chan->done_list); in xilinx_dma_free_descriptors()
921 xilinx_dma_free_desc_list(chan, &chan->active_list); in xilinx_dma_free_descriptors()
923 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_descriptors()
932 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_free_chan_resources() local
935 dev_dbg(chan->dev, "Free all channel resources.\n"); in xilinx_dma_free_chan_resources()
937 xilinx_dma_free_descriptors(chan); in xilinx_dma_free_chan_resources()
939 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_chan_resources()
940 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
941 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
942 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
945 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_free_chan_resources()
946 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_free_chan_resources()
947 chan->seg_p); in xilinx_dma_free_chan_resources()
950 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), in xilinx_dma_free_chan_resources()
951 chan->cyclic_seg_v, chan->cyclic_seg_p); in xilinx_dma_free_chan_resources()
954 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
955 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
956 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
957 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
960 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * in xilinx_dma_free_chan_resources()
961 XILINX_DMA_NUM_DESCS, chan->seg_mv, in xilinx_dma_free_chan_resources()
962 chan->seg_p); in xilinx_dma_free_chan_resources()
965 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && in xilinx_dma_free_chan_resources()
966 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
967 dma_pool_destroy(chan->desc_pool); in xilinx_dma_free_chan_resources()
968 chan->desc_pool = NULL; in xilinx_dma_free_chan_resources()
980 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, in xilinx_dma_get_residue() argument
993 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_get_residue()
999 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
1000 } else if (chan->xdev->dma_config->dmatype == in xilinx_dma_get_residue()
1007 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
1016 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
1029 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, in xilinx_dma_chan_handle_cyclic() argument
1037 spin_unlock_irqrestore(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1039 spin_lock_irqsave(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1047 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) in xilinx_dma_chan_desc_cleanup() argument
1052 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1054 list_for_each_entry_safe(desc, next, &chan->done_list, node) { in xilinx_dma_chan_desc_cleanup()
1058 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); in xilinx_dma_chan_desc_cleanup()
1066 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_dma_chan_desc_cleanup()
1077 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1079 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1083 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_chan_desc_cleanup()
1089 if (chan->terminating) in xilinx_dma_chan_desc_cleanup()
1093 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1102 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); in xilinx_dma_do_tasklet() local
1104 xilinx_dma_chan_desc_cleanup(chan); in xilinx_dma_do_tasklet()
1115 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_alloc_chan_resources() local
1119 if (chan->desc_pool) in xilinx_dma_alloc_chan_resources()
1126 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1128 chan->seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1129 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, in xilinx_dma_alloc_chan_resources()
1130 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1131 if (!chan->seg_v) { in xilinx_dma_alloc_chan_resources()
1132 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1134 chan->id); in xilinx_dma_alloc_chan_resources()
1143 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1144 sizeof(*chan->cyclic_seg_v), in xilinx_dma_alloc_chan_resources()
1145 &chan->cyclic_seg_p, in xilinx_dma_alloc_chan_resources()
1147 if (!chan->cyclic_seg_v) { in xilinx_dma_alloc_chan_resources()
1148 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1150 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1151 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_alloc_chan_resources()
1152 chan->seg_p); in xilinx_dma_alloc_chan_resources()
1155 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; in xilinx_dma_alloc_chan_resources()
1158 chan->seg_v[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1159 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1161 chan->seg_v[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1162 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1164 chan->seg_v[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1165 sizeof(*chan->seg_v) * i; in xilinx_dma_alloc_chan_resources()
1166 list_add_tail(&chan->seg_v[i].node, in xilinx_dma_alloc_chan_resources()
1167 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1169 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_alloc_chan_resources()
1171 chan->seg_mv = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1172 sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1174 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1175 if (!chan->seg_mv) { in xilinx_dma_alloc_chan_resources()
1176 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1178 chan->id); in xilinx_dma_alloc_chan_resources()
1182 chan->seg_mv[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1183 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1185 chan->seg_mv[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1186 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1188 chan->seg_mv[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1189 sizeof(*chan->seg_mv) * i; in xilinx_dma_alloc_chan_resources()
1190 list_add_tail(&chan->seg_mv[i].node, in xilinx_dma_alloc_chan_resources()
1191 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1193 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_alloc_chan_resources()
1194 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1195 chan->dev, in xilinx_dma_alloc_chan_resources()
1200 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1201 chan->dev, in xilinx_dma_alloc_chan_resources()
1207 if (!chan->desc_pool && in xilinx_dma_alloc_chan_resources()
1208 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && in xilinx_dma_alloc_chan_resources()
1209 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { in xilinx_dma_alloc_chan_resources()
1210 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1212 chan->id); in xilinx_dma_alloc_chan_resources()
1218 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1222 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_alloc_chan_resources()
1226 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_alloc_chan_resources()
1227 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_alloc_chan_resources()
1241 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, in xilinx_dma_calc_copysize() argument
1247 chan->xdev->max_buffer_len); in xilinx_dma_calc_copysize()
1250 chan->xdev->common.copy_align) { in xilinx_dma_calc_copysize()
1256 (1 << chan->xdev->common.copy_align)); in xilinx_dma_calc_copysize()
1273 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_tx_status() local
1283 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_status()
1284 if (!list_empty(&chan->active_list)) { in xilinx_dma_tx_status()
1285 desc = list_last_entry(&chan->active_list, in xilinx_dma_tx_status()
1291 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) in xilinx_dma_tx_status()
1292 residue = xilinx_dma_get_residue(chan, desc); in xilinx_dma_tx_status()
1294 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_status()
1307 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) in xilinx_dma_stop_transfer() argument
1311 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); in xilinx_dma_stop_transfer()
1314 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_dma_stop_transfer()
1325 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) in xilinx_cdma_stop_transfer() argument
1329 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_cdma_stop_transfer()
1338 static void xilinx_dma_start(struct xilinx_dma_chan *chan) in xilinx_dma_start() argument
1343 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); in xilinx_dma_start()
1346 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_dma_start()
1351 dev_err(chan->dev, "Cannot start channel %p: %x\n", in xilinx_dma_start()
1352 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_start()
1354 chan->err = true; in xilinx_dma_start()
1362 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_vdma_start_transfer() argument
1364 struct xilinx_vdma_config *config = &chan->config; in xilinx_vdma_start_transfer()
1371 if (chan->err) in xilinx_vdma_start_transfer()
1374 if (!chan->idle) in xilinx_vdma_start_transfer()
1377 if (list_empty(&chan->pending_list)) in xilinx_vdma_start_transfer()
1380 desc = list_first_entry(&chan->pending_list, in xilinx_vdma_start_transfer()
1384 if (chan->has_vflip) { in xilinx_vdma_start_transfer()
1385 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); in xilinx_vdma_start_transfer()
1388 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, in xilinx_vdma_start_transfer()
1392 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_start_transfer()
1405 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_vdma_start_transfer()
1407 j = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1408 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); in xilinx_vdma_start_transfer()
1409 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_vdma_start_transfer()
1416 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); in xilinx_vdma_start_transfer()
1419 xilinx_dma_start(chan); in xilinx_vdma_start_transfer()
1421 if (chan->err) in xilinx_vdma_start_transfer()
1425 if (chan->desc_submitcount < chan->num_frms) in xilinx_vdma_start_transfer()
1426 i = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1429 if (chan->ext_addr) in xilinx_vdma_start_transfer()
1430 vdma_desc_write_64(chan, in xilinx_vdma_start_transfer()
1435 vdma_desc_write(chan, in xilinx_vdma_start_transfer()
1446 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); in xilinx_vdma_start_transfer()
1447 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, in xilinx_vdma_start_transfer()
1449 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); in xilinx_vdma_start_transfer()
1451 chan->desc_submitcount++; in xilinx_vdma_start_transfer()
1452 chan->desc_pendingcount--; in xilinx_vdma_start_transfer()
1453 list_move_tail(&desc->node, &chan->active_list); in xilinx_vdma_start_transfer()
1454 if (chan->desc_submitcount == chan->num_frms) in xilinx_vdma_start_transfer()
1455 chan->desc_submitcount = 0; in xilinx_vdma_start_transfer()
1457 chan->idle = false; in xilinx_vdma_start_transfer()
1464 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_cdma_start_transfer() argument
1468 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); in xilinx_cdma_start_transfer()
1470 if (chan->err) in xilinx_cdma_start_transfer()
1473 if (!chan->idle) in xilinx_cdma_start_transfer()
1476 if (list_empty(&chan->pending_list)) in xilinx_cdma_start_transfer()
1479 head_desc = list_first_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1481 tail_desc = list_last_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1486 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_cdma_start_transfer()
1488 ctrl_reg |= chan->desc_pendingcount << in xilinx_cdma_start_transfer()
1490 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); in xilinx_cdma_start_transfer()
1493 if (chan->has_sg) { in xilinx_cdma_start_transfer()
1494 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, in xilinx_cdma_start_transfer()
1497 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_cdma_start_transfer()
1500 xilinx_write(chan, XILINX_DMA_REG_CURDESC, in xilinx_cdma_start_transfer()
1504 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, in xilinx_cdma_start_transfer()
1517 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, in xilinx_cdma_start_transfer()
1519 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, in xilinx_cdma_start_transfer()
1523 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, in xilinx_cdma_start_transfer()
1524 hw->control & chan->xdev->max_buffer_len); in xilinx_cdma_start_transfer()
1527 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_cdma_start_transfer()
1528 chan->desc_pendingcount = 0; in xilinx_cdma_start_transfer()
1529 chan->idle = false; in xilinx_cdma_start_transfer()
1536 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_dma_start_transfer() argument
1542 if (chan->err) in xilinx_dma_start_transfer()
1545 if (list_empty(&chan->pending_list)) in xilinx_dma_start_transfer()
1548 if (!chan->idle) in xilinx_dma_start_transfer()
1551 head_desc = list_first_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1553 tail_desc = list_last_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1558 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_start_transfer()
1560 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_dma_start_transfer()
1562 reg |= chan->desc_pendingcount << in xilinx_dma_start_transfer()
1564 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_start_transfer()
1567 if (chan->has_sg) in xilinx_dma_start_transfer()
1568 xilinx_write(chan, XILINX_DMA_REG_CURDESC, in xilinx_dma_start_transfer()
1571 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; in xilinx_dma_start_transfer()
1572 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_start_transfer()
1574 xilinx_dma_start(chan); in xilinx_dma_start_transfer()
1576 if (chan->err) in xilinx_dma_start_transfer()
1580 if (chan->has_sg) { in xilinx_dma_start_transfer()
1581 if (chan->cyclic) in xilinx_dma_start_transfer()
1582 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, in xilinx_dma_start_transfer()
1583 chan->cyclic_seg_v->phys); in xilinx_dma_start_transfer()
1585 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, in xilinx_dma_start_transfer()
1596 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, in xilinx_dma_start_transfer()
1600 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, in xilinx_dma_start_transfer()
1601 hw->control & chan->xdev->max_buffer_len); in xilinx_dma_start_transfer()
1604 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_dma_start_transfer()
1605 chan->desc_pendingcount = 0; in xilinx_dma_start_transfer()
1606 chan->idle = false; in xilinx_dma_start_transfer()
1613 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_mcdma_start_transfer() argument
1624 if (chan->err) in xilinx_mcdma_start_transfer()
1627 if (!chan->idle) in xilinx_mcdma_start_transfer()
1630 if (list_empty(&chan->pending_list)) in xilinx_mcdma_start_transfer()
1633 head_desc = list_first_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1635 tail_desc = list_last_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1640 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1642 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { in xilinx_mcdma_start_transfer()
1644 reg |= chan->desc_pendingcount << in xilinx_mcdma_start_transfer()
1649 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1652 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1656 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); in xilinx_mcdma_start_transfer()
1657 reg |= BIT(chan->tdest); in xilinx_mcdma_start_transfer()
1658 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); in xilinx_mcdma_start_transfer()
1661 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1663 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1665 xilinx_dma_start(chan); in xilinx_mcdma_start_transfer()
1667 if (chan->err) in xilinx_mcdma_start_transfer()
1671 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1674 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_mcdma_start_transfer()
1675 chan->desc_pendingcount = 0; in xilinx_mcdma_start_transfer()
1676 chan->idle = false; in xilinx_mcdma_start_transfer()
1685 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_issue_pending() local
1688 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_issue_pending()
1689 chan->start_transfer(chan); in xilinx_dma_issue_pending()
1690 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_issue_pending()
1712 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) in xilinx_dma_complete_descriptor() argument
1717 if (list_empty(&chan->active_list)) in xilinx_dma_complete_descriptor()
1720 list_for_each_entry_safe(desc, next, &chan->active_list, node) { in xilinx_dma_complete_descriptor()
1721 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_complete_descriptor()
1726 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) in xilinx_dma_complete_descriptor()
1729 if (chan->has_sg && chan->xdev->dma_config->dmatype != in xilinx_dma_complete_descriptor()
1731 desc->residue = xilinx_dma_get_residue(chan, desc); in xilinx_dma_complete_descriptor()
1734 desc->err = chan->err; in xilinx_dma_complete_descriptor()
1739 list_add_tail(&desc->node, &chan->done_list); in xilinx_dma_complete_descriptor()
1749 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) in xilinx_dma_reset() argument
1754 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); in xilinx_dma_reset()
1757 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, in xilinx_dma_reset()
1762 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", in xilinx_dma_reset()
1763 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), in xilinx_dma_reset()
1764 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_reset()
1768 chan->err = false; in xilinx_dma_reset()
1769 chan->idle = true; in xilinx_dma_reset()
1770 chan->desc_pendingcount = 0; in xilinx_dma_reset()
1771 chan->desc_submitcount = 0; in xilinx_dma_reset()
1782 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) in xilinx_dma_chan_reset() argument
1787 err = xilinx_dma_reset(chan); in xilinx_dma_chan_reset()
1792 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_chan_reset()
1807 struct xilinx_dma_chan *chan = data; in xilinx_mcdma_irq_handler() local
1810 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1816 chan_sermask = dma_ctrl_read(chan, ser_offset); in xilinx_mcdma_irq_handler()
1822 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1823 chan_offset = chan->xdev->dma_config->max_channels / 2; in xilinx_mcdma_irq_handler()
1826 chan = chan->xdev->chan[chan_offset]; in xilinx_mcdma_irq_handler()
1828 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); in xilinx_mcdma_irq_handler()
1832 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), in xilinx_mcdma_irq_handler()
1836 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", in xilinx_mcdma_irq_handler()
1837 chan, in xilinx_mcdma_irq_handler()
1838 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), in xilinx_mcdma_irq_handler()
1839 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET in xilinx_mcdma_irq_handler()
1840 (chan->tdest)), in xilinx_mcdma_irq_handler()
1841 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET in xilinx_mcdma_irq_handler()
1842 (chan->tdest))); in xilinx_mcdma_irq_handler()
1843 chan->err = true; in xilinx_mcdma_irq_handler()
1851 dev_dbg(chan->dev, "Inter-packet latency too long\n"); in xilinx_mcdma_irq_handler()
1855 spin_lock(&chan->lock); in xilinx_mcdma_irq_handler()
1856 xilinx_dma_complete_descriptor(chan); in xilinx_mcdma_irq_handler()
1857 chan->idle = true; in xilinx_mcdma_irq_handler()
1858 chan->start_transfer(chan); in xilinx_mcdma_irq_handler()
1859 spin_unlock(&chan->lock); in xilinx_mcdma_irq_handler()
1862 tasklet_hi_schedule(&chan->tasklet); in xilinx_mcdma_irq_handler()
1875 struct xilinx_dma_chan *chan = data; in xilinx_dma_irq_handler() local
1879 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); in xilinx_dma_irq_handler()
1883 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, in xilinx_dma_irq_handler()
1896 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, in xilinx_dma_irq_handler()
1899 if (!chan->flush_on_fsync || in xilinx_dma_irq_handler()
1901 dev_err(chan->dev, in xilinx_dma_irq_handler()
1903 chan, errors, in xilinx_dma_irq_handler()
1904 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), in xilinx_dma_irq_handler()
1905 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); in xilinx_dma_irq_handler()
1906 chan->err = true; in xilinx_dma_irq_handler()
1912 spin_lock(&chan->lock); in xilinx_dma_irq_handler()
1913 xilinx_dma_complete_descriptor(chan); in xilinx_dma_irq_handler()
1914 chan->idle = true; in xilinx_dma_irq_handler()
1915 chan->start_transfer(chan); in xilinx_dma_irq_handler()
1916 spin_unlock(&chan->lock); in xilinx_dma_irq_handler()
1919 tasklet_schedule(&chan->tasklet); in xilinx_dma_irq_handler()
1928 static void append_desc_queue(struct xilinx_dma_chan *chan, in append_desc_queue() argument
1937 if (list_empty(&chan->pending_list)) in append_desc_queue()
1944 tail_desc = list_last_entry(&chan->pending_list, in append_desc_queue()
1946 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in append_desc_queue()
1951 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in append_desc_queue()
1956 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in append_desc_queue()
1974 list_add_tail(&desc->node, &chan->pending_list); in append_desc_queue()
1975 chan->desc_pendingcount++; in append_desc_queue()
1977 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) in append_desc_queue()
1978 && unlikely(chan->desc_pendingcount > chan->num_frms)) { in append_desc_queue()
1979 dev_dbg(chan->dev, "desc pendingcount is too high\n"); in append_desc_queue()
1980 chan->desc_pendingcount = chan->num_frms; in append_desc_queue()
1993 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); in xilinx_dma_tx_submit() local
1998 if (chan->cyclic) { in xilinx_dma_tx_submit()
1999 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_tx_submit()
2003 if (chan->err) { in xilinx_dma_tx_submit()
2008 err = xilinx_dma_chan_reset(chan); in xilinx_dma_tx_submit()
2013 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_submit()
2018 append_desc_queue(chan, desc); in xilinx_dma_tx_submit()
2021 chan->cyclic = true; in xilinx_dma_tx_submit()
2023 chan->terminating = false; in xilinx_dma_tx_submit()
2025 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_submit()
2044 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_vdma_dma_prep_interleaved() local
2063 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_vdma_dma_prep_interleaved()
2067 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_vdma_dma_prep_interleaved()
2072 segment = xilinx_vdma_alloc_tx_segment(chan); in xilinx_vdma_dma_prep_interleaved()
2082 hw->stride |= chan->config.frm_dly << in xilinx_vdma_dma_prep_interleaved()
2086 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2093 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2112 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_vdma_dma_prep_interleaved()
2130 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_cdma_prep_memcpy() local
2135 if (!len || len > chan->xdev->max_buffer_len) in xilinx_cdma_prep_memcpy()
2138 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_cdma_prep_memcpy()
2142 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_cdma_prep_memcpy()
2146 segment = xilinx_cdma_alloc_tx_segment(chan); in xilinx_cdma_prep_memcpy()
2154 if (chan->ext_addr) { in xilinx_cdma_prep_memcpy()
2168 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_cdma_prep_memcpy()
2188 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_prep_slave_sg() local
2201 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_dma_prep_slave_sg()
2205 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_slave_sg()
2217 segment = xilinx_axidma_alloc_tx_segment(chan); in xilinx_dma_prep_slave_sg()
2225 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), in xilinx_dma_prep_slave_sg()
2230 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), in xilinx_dma_prep_slave_sg()
2235 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2256 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2264 if (chan->xdev->has_axistream_connected) in xilinx_dma_prep_slave_sg()
2270 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_prep_slave_sg()
2290 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_prep_dma_cyclic() local
2310 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_dma_prep_dma_cyclic()
2314 chan->direction = direction; in xilinx_dma_prep_dma_cyclic()
2315 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_dma_cyclic()
2325 segment = xilinx_axidma_alloc_tx_segment(chan); in xilinx_dma_prep_dma_cyclic()
2333 copy = xilinx_dma_calc_copysize(chan, period_len, in xilinx_dma_prep_dma_cyclic()
2336 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, in xilinx_dma_prep_dma_cyclic()
2359 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_prep_dma_cyclic()
2361 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_prep_dma_cyclic()
2377 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_prep_dma_cyclic()
2398 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_mcdma_prep_slave_sg() local
2411 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_mcdma_prep_slave_sg()
2415 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_mcdma_prep_slave_sg()
2427 segment = xilinx_aximcdma_alloc_tx_segment(chan); in xilinx_mcdma_prep_slave_sg()
2436 chan->xdev->max_buffer_len); in xilinx_mcdma_prep_slave_sg()
2440 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), in xilinx_mcdma_prep_slave_sg()
2444 if (chan->direction == DMA_MEM_TO_DEV && app_w) { in xilinx_mcdma_prep_slave_sg()
2463 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_mcdma_prep_slave_sg()
2474 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_mcdma_prep_slave_sg()
2487 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_terminate_all() local
2491 if (!chan->cyclic) { in xilinx_dma_terminate_all()
2492 err = chan->stop_transfer(chan); in xilinx_dma_terminate_all()
2494 dev_err(chan->dev, "Cannot stop channel %p: %x\n", in xilinx_dma_terminate_all()
2495 chan, dma_ctrl_read(chan, in xilinx_dma_terminate_all()
2497 chan->err = true; in xilinx_dma_terminate_all()
2501 xilinx_dma_chan_reset(chan); in xilinx_dma_terminate_all()
2503 chan->terminating = true; in xilinx_dma_terminate_all()
2504 xilinx_dma_free_descriptors(chan); in xilinx_dma_terminate_all()
2505 chan->idle = true; in xilinx_dma_terminate_all()
2507 if (chan->cyclic) { in xilinx_dma_terminate_all()
2508 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_terminate_all()
2510 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_terminate_all()
2511 chan->cyclic = false; in xilinx_dma_terminate_all()
2514 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_terminate_all()
2515 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_terminate_all()
2523 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_synchronize() local
2525 tasklet_kill(&chan->tasklet); in xilinx_dma_synchronize()
2544 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_vdma_channel_set_config() local
2548 return xilinx_dma_chan_reset(chan); in xilinx_vdma_channel_set_config()
2550 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2552 chan->config.frm_dly = cfg->frm_dly; in xilinx_vdma_channel_set_config()
2553 chan->config.park = cfg->park; in xilinx_vdma_channel_set_config()
2556 chan->config.gen_lock = cfg->gen_lock; in xilinx_vdma_channel_set_config()
2557 chan->config.master = cfg->master; in xilinx_vdma_channel_set_config()
2560 if (cfg->gen_lock && chan->genlock) { in xilinx_vdma_channel_set_config()
2566 chan->config.frm_cnt_en = cfg->frm_cnt_en; in xilinx_vdma_channel_set_config()
2567 chan->config.vflip_en = cfg->vflip_en; in xilinx_vdma_channel_set_config()
2570 chan->config.park_frm = cfg->park_frm; in xilinx_vdma_channel_set_config()
2572 chan->config.park_frm = -1; in xilinx_vdma_channel_set_config()
2574 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2575 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2580 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2586 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2593 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); in xilinx_vdma_channel_set_config()
2607 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) in xilinx_dma_chan_remove() argument
2610 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_chan_remove()
2613 if (chan->irq > 0) in xilinx_dma_chan_remove()
2614 free_irq(chan->irq, chan); in xilinx_dma_chan_remove()
2616 tasklet_kill(&chan->tasklet); in xilinx_dma_chan_remove()
2618 list_del(&chan->common.device_node); in xilinx_dma_chan_remove()
2812 struct xilinx_dma_chan *chan; in xilinx_dma_chan_probe() local
2818 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); in xilinx_dma_chan_probe()
2819 if (!chan) in xilinx_dma_chan_probe()
2822 chan->dev = xdev->dev; in xilinx_dma_chan_probe()
2823 chan->xdev = xdev; in xilinx_dma_chan_probe()
2824 chan->desc_pendingcount = 0x0; in xilinx_dma_chan_probe()
2825 chan->ext_addr = xdev->ext_addr; in xilinx_dma_chan_probe()
2831 chan->idle = true; in xilinx_dma_chan_probe()
2833 spin_lock_init(&chan->lock); in xilinx_dma_chan_probe()
2834 INIT_LIST_HEAD(&chan->pending_list); in xilinx_dma_chan_probe()
2835 INIT_LIST_HEAD(&chan->done_list); in xilinx_dma_chan_probe()
2836 INIT_LIST_HEAD(&chan->active_list); in xilinx_dma_chan_probe()
2837 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_chan_probe()
2842 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); in xilinx_dma_chan_probe()
2844 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); in xilinx_dma_chan_probe()
2863 chan->direction = DMA_MEM_TO_DEV; in xilinx_dma_chan_probe()
2864 chan->id = xdev->mm2s_chan_id++; in xilinx_dma_chan_probe()
2865 chan->tdest = chan->id; in xilinx_dma_chan_probe()
2867 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; in xilinx_dma_chan_probe()
2869 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; in xilinx_dma_chan_probe()
2870 chan->config.park = 1; in xilinx_dma_chan_probe()
2874 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2880 chan->direction = DMA_DEV_TO_MEM; in xilinx_dma_chan_probe()
2881 chan->id = xdev->s2mm_chan_id++; in xilinx_dma_chan_probe()
2882 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; in xilinx_dma_chan_probe()
2883 chan->has_vflip = of_property_read_bool(node, in xilinx_dma_chan_probe()
2885 if (chan->has_vflip) { in xilinx_dma_chan_probe()
2886 chan->config.vflip_en = dma_read(chan, in xilinx_dma_chan_probe()
2892 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2894 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2897 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; in xilinx_dma_chan_probe()
2898 chan->config.park = 1; in xilinx_dma_chan_probe()
2902 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2910 chan->irq = of_irq_get(node, chan->tdest); in xilinx_dma_chan_probe()
2911 if (chan->irq < 0) in xilinx_dma_chan_probe()
2912 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); in xilinx_dma_chan_probe()
2913 err = request_irq(chan->irq, xdev->dma_config->irq_handler, in xilinx_dma_chan_probe()
2914 IRQF_SHARED, "xilinx-dma-controller", chan); in xilinx_dma_chan_probe()
2916 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); in xilinx_dma_chan_probe()
2921 chan->start_transfer = xilinx_dma_start_transfer; in xilinx_dma_chan_probe()
2922 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2924 chan->start_transfer = xilinx_mcdma_start_transfer; in xilinx_dma_chan_probe()
2925 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2927 chan->start_transfer = xilinx_cdma_start_transfer; in xilinx_dma_chan_probe()
2928 chan->stop_transfer = xilinx_cdma_stop_transfer; in xilinx_dma_chan_probe()
2930 chan->start_transfer = xilinx_vdma_start_transfer; in xilinx_dma_chan_probe()
2931 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2937 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & in xilinx_dma_chan_probe()
2939 chan->has_sg = true; in xilinx_dma_chan_probe()
2940 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, in xilinx_dma_chan_probe()
2941 chan->has_sg ? "enabled" : "disabled"); in xilinx_dma_chan_probe()
2945 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); in xilinx_dma_chan_probe()
2951 chan->common.device = &xdev->common; in xilinx_dma_chan_probe()
2953 list_add_tail(&chan->common.device_node, &xdev->common.channels); in xilinx_dma_chan_probe()
2954 xdev->chan[chan->id] = chan; in xilinx_dma_chan_probe()
2957 err = xilinx_dma_chan_reset(chan); in xilinx_dma_chan_probe()
3008 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) in of_dma_xilinx_xlate()
3011 return dma_get_slave_channel(&xdev->chan[chan_id]->common); in of_dma_xilinx_xlate()
3208 if (xdev->chan[i]) in xilinx_dma_probe()
3209 xdev->chan[i]->num_frms = num_frames; in xilinx_dma_probe()
3240 if (xdev->chan[i]) in xilinx_dma_probe()
3241 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_probe()
3262 if (xdev->chan[i]) in xilinx_dma_remove()
3263 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_remove()