Lines Matching refs:dimm
1107 int dimm, size0, size1; in dct_debug_display_dimm_sizes() local
1133 for (dimm = 0; dimm < 4; dimm++) { in dct_debug_display_dimm_sizes()
1135 if (dcsb[dimm * 2] & DCSB_CS_ENABLE) in dct_debug_display_dimm_sizes()
1143 DBAM_DIMM(dimm, dbam), in dct_debug_display_dimm_sizes()
1144 dimm); in dct_debug_display_dimm_sizes()
1147 if (dcsb[dimm * 2 + 1] & DCSB_CS_ENABLE) in dct_debug_display_dimm_sizes()
1149 DBAM_DIMM(dimm, dbam), in dct_debug_display_dimm_sizes()
1150 dimm); in dct_debug_display_dimm_sizes()
1153 dimm * 2, size0, in dct_debug_display_dimm_sizes()
1154 dimm * 2 + 1, size1); in dct_debug_display_dimm_sizes()
1200 static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) in umc_get_cs_mode() argument
1205 if (csrow_enabled(2 * dimm, ctrl, pvt)) in umc_get_cs_mode()
1208 if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) in umc_get_cs_mode()
1212 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) in umc_get_cs_mode()
1233 int csrow_nr, int dimm) in __addr_mask_to_cs_size() argument
1257 edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm); in __addr_mask_to_cs_size()
1273 int dimm, size = 0; in umc_addr_mask_to_cs_size() local
1305 dimm = csrow_nr >> 1; in umc_addr_mask_to_cs_size()
1316 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm); in umc_addr_mask_to_cs_size()
1321 int dimm, size0, size1, cs0, cs1, cs_mode; in umc_debug_display_dimm_sizes() local
1325 for (dimm = 0; dimm < 2; dimm++) { in umc_debug_display_dimm_sizes()
1326 cs0 = dimm * 2; in umc_debug_display_dimm_sizes()
1327 cs1 = dimm * 2 + 1; in umc_debug_display_dimm_sizes()
1329 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt); in umc_debug_display_dimm_sizes()
3073 struct dimm_info *dimm; in umc_init_csrows() local
3094 dimm = mci->csrows[cs]->channels[umc]->dimm; in umc_init_csrows()
3099 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs); in umc_init_csrows()
3100 dimm->mtype = pvt->umc[umc].dram_type; in umc_init_csrows()
3101 dimm->edac_mode = edac_mode; in umc_init_csrows()
3102 dimm->dtype = dev_type; in umc_init_csrows()
3103 dimm->grain = 64; in umc_init_csrows()
3117 struct dimm_info *dimm; in dct_init_csrows() local
3150 csrow->channels[0]->dimm->nr_pages = nr_pages; in dct_init_csrows()
3157 csrow->channels[1]->dimm->nr_pages = row_dct1_pages; in dct_init_csrows()
3171 dimm = csrow->channels[j]->dimm; in dct_init_csrows()
3172 dimm->mtype = pvt->dram_type; in dct_init_csrows()
3173 dimm->edac_mode = edac_mode; in dct_init_csrows()
3174 dimm->grain = 64; in dct_init_csrows()
3583 struct dimm_info *dimm; in gpu_init_csrows() local
3591 dimm = mci->csrows[umc]->channels[cs]->dimm; in gpu_init_csrows()
3596 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs); in gpu_init_csrows()
3597 dimm->edac_mode = EDAC_SECDED; in gpu_init_csrows()
3598 dimm->mtype = pvt->dram_type; in gpu_init_csrows()
3599 dimm->dtype = DEV_X16; in gpu_init_csrows()
3600 dimm->grain = 64; in gpu_init_csrows()